bk://bk.arm.linux.org.uk/linux-2.6-rmk nico@org.rmk.(none)|ChangeSet|20040404213425|43229 nico # This is a BitKeeper generated diff -Nru style patch. # # ChangeSet # 2004/04/04 16:01:39-07:00 akpm@bix.(none) # Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk # into bix.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/04/04 16:01:36-07:00 akpm@bix.(none) +0 -0 # Auto merged # # ChangeSet # 2004/04/04 22:34:25+01:00 nico@org.rmk.(none) # [ARM PATCH] 1783/1: more PXA reg definitions # # Patch from Nicolas Pitre # # # include/asm-arm/arch-pxa/pxa-regs.h # 2003/12/15 01:07:42+00:00 nico@org.rmk.(none) +29 -0 # [PATCH] 1783/1: more PXA reg definitions # # ChangeSet # 2004/04/04 22:08:18+01:00 nico@org.rmk.(none) # [ARM PATCH] 1782/1: discontigmem support for PXA chips # # Patch from Nicolas Pitre # # # include/asm-arm/arch-pxa/memory.h # 2004/03/26 16:57:59+00:00 nico@org.rmk.(none) +48 -0 # [PATCH] 1782/1: discontigmem support for PXA chips # # ChangeSet # 2004/04/04 13:40:31+01:00 tony@com.rmk.(none) # [ARM PATCH] 1781/1: Add TI OMAP support, arch files # # Patch from Tony Lindgren # # This patch adds the arch files for Texas Instruments OMAP-1510 and # 1610 processors. # # OMAP is an embedded ARM processor with integrated DSP. # # OMAP-1610 has hardware support for USB OTG, which might be of interest # to Linux developers. OMAP-1610 could be easily be used as development # platform to add USB OTG support to Linux. # # This patch is an updated version of patch 1769/1 with Russell King's # comments fixed. This patch requires patch 1777/1 applied. # # This patch is brought to you by various linux-omap developers. # # arch/arm/mach-omap/omap-perseus2.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +116 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/ocpi.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +116 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/mux.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +124 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/leds.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +2 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/leds.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +23 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/leds-perseus2.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +103 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/leds-innovator.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +103 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/irq.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +224 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/innovator1610.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +91 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/gpio.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +755 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/fpga.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +209 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/dma.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +560 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/clocks.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +676 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/bus.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +280 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/Kconfig # 2004/03/24 19:22:11+00:00 tony@com.rmk.(none) +113 -3 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/omap-perseus2.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/omap-perseus2.c # # arch/arm/mach-omap/omap-generic.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +77 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/ocpi.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/ocpi.c # # arch/arm/mach-omap/mux.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/mux.c # # arch/arm/mach-omap/leds.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds.h # # arch/arm/mach-omap/leds.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds.c # # arch/arm/mach-omap/leds-perseus2.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds-perseus2.c # # arch/arm/mach-omap/leds-innovator.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds-innovator.c # # arch/arm/mach-omap/irq.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/irq.c # # arch/arm/mach-omap/innovator1610.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/innovator1610.c # # arch/arm/mach-omap/innovator1510.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +99 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/gpio.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/gpio.c # # arch/arm/mach-omap/fpga.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/fpga.c # # arch/arm/mach-omap/dma.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/dma.c # # arch/arm/mach-omap/common.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +6 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/common.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +69 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/clocks.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/clocks.c # # arch/arm/mach-omap/bus.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/bus.c # # arch/arm/mach-omap/omap-generic.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/omap-generic.c # # arch/arm/mach-omap/innovator1510.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/innovator1510.c # # arch/arm/mach-omap/common.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/common.h # # arch/arm/mach-omap/common.c # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/common.c # # arch/arm/mach-omap/Makefile # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +36 -0 # [PATCH] 1781/1: Add TI OMAP support, arch files # # arch/arm/mach-omap/Makefile # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/Makefile # # ChangeSet # 2004/04/04 13:36:50+01:00 tony@com.rmk.(none) # [ARM PATCH] 1780/1: Add TI OMAP support, include files # # Patch from Tony Lindgren # # This patch adds the include files for Texas Instruments OMAP-1510 and # 1610 processors. # # OMAP is an embedded ARM processor with integrated DSP. # # OMAP-1610 has hardware support for USB OTG, which might be of interest # to Linux developers. OMAP-1610 could be easily be used as development # platform to add USB OTG support to Linux. # # This patch is an updated version of patch 1768/1 with Russell King's # comments fixed. This patch requires patch 1777/1 applied. # # This patch is brought to you by various linux-omap developers. # # include/asm-arm/arch-omap/serial.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +167 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/pm.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +150 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/mux.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +462 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/fpga.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +26 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/vmalloc.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/uncompress.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +76 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/timex.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/time.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +212 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/system.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +20 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/serial.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/serial.h # # include/asm-arm/arch-omap/pm.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/pm.h # # include/asm-arm/arch-omap/param.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +24 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap-perseus2.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +152 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap-h2.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/mux.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/mux.h # # include/asm-arm/arch-omap/memory.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +92 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/irqs.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +262 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/io.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +24 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/hardware.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +327 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/gpio.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +68 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/fpga.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/fpga.h # # include/asm-arm/arch-omap/dma.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +224 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/clocks.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +216 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/bus.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +97 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/vmalloc.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/vmalloc.h # # include/asm-arm/arch-omap/uncompress.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/uncompress.h # # include/asm-arm/arch-omap/timex.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/timex.h # # include/asm-arm/arch-omap/time.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/time.h # # include/asm-arm/arch-omap/system.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/system.h # # include/asm-arm/arch-omap/param.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/param.h # # include/asm-arm/arch-omap/omap1610.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +73 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap1510.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +54 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap-perseus2.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-perseus2.h # # include/asm-arm/arch-omap/omap-innovator.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +214 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap-h2.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-h2.h # # include/asm-arm/arch-omap/memory.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/memory.h # # include/asm-arm/arch-omap/irqs.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/irqs.h # # include/asm-arm/arch-omap/io.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/io.h # # include/asm-arm/arch-omap/hardware.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/hardware.h # # include/asm-arm/arch-omap/gpio.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/gpio.h # # include/asm-arm/arch-omap/dma.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/dma.h # # include/asm-arm/arch-omap/clocks.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/clocks.h # # include/asm-arm/arch-omap/bus.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/bus.h # # include/asm-arm/arch-omap/omap1610.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap1610.h # # include/asm-arm/arch-omap/omap1510.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap1510.h # # include/asm-arm/arch-omap/omap-innovator.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-innovator.h # # include/asm-arm/arch-omap/omap730.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +50 -0 # [PATCH] 1780/1: Add TI OMAP support, include files # # include/asm-arm/arch-omap/omap730.h # 2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap730.h # # ChangeSet # 2004/04/04 13:32:38+01:00 tony@com.rmk.(none) # [ARM PATCH] 1777/1: Add TI OMAP support to ARM core files # # Patch from Tony Lindgren # # This patch updates the ARM Linux core files to add support for # Texas Instruments OMAP-1510, 1610, and 730 processors. # # OMAP is an embedded ARM processor with integrated DSP. # # OMAP-1610 has hardware support for USB OTG, which might be of interest # to Linux developers. OMAP-1610 could be easily be used as development # platform to add USB OTG support to Linux. # # This patch is an updated version of an earlier patch 1767/1 # with the dummy Kconfig added for OMAP as suggested by Russell King # here: # # http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=1767/1 # # This patch is brought to you by various linux-omap developers. # # include/asm-arm/proc-fns.h # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +8 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # include/asm-arm/cacheflush.h # 2004/03/15 17:01:34+00:00 tony@com.rmk.(none) +1 -1 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/mm/tlb-v4wbi.S # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +1 -1 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/kernel/entry-armv.S # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +27 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/kernel/debug.S # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +26 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/boot/Makefile # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +3 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/Makefile # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +2 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/Kconfig # 2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +7 -2 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/mach-omap/Kconfig # 2004/03/16 01:08:17+00:00 tony@com.rmk.(none) +3 -0 # [PATCH] 1777/1: Add TI OMAP support to ARM core files # # arch/arm/mach-omap/Kconfig # 2004/03/16 01:08:17+00:00 tony@com.rmk.(none) +0 -0 # BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/Kconfig # # ChangeSet # 2004/03/27 02:24:52-08:00 akpm@bix.(none) # Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk # into bix.(none):/usr/src/dead-bk-arm # # arch/arm/Kconfig # 2004/03/27 02:24:49-08:00 akpm@bix.(none) +0 -0 # Auto merged # # ChangeSet # 2004/03/25 10:54:20-08:00 akpm@bix.(none) # Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk # into bix.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/03/25 10:54:18-08:00 akpm@bix.(none) +0 -0 # Auto merged # # ChangeSet # 2004/03/19 10:00:02-08:00 akpm@bix.(none) # Merge bix.(none):/usr/src/bk25 into bix.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/03/19 09:59:59-08:00 akpm@bix.(none) +0 -0 # Auto merged # # ChangeSet # 2004/03/15 22:29:04-08:00 akpm@bix.(none) # Merge bix.(none):/usr/src/bk25 into bix.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/03/15 22:28:51-08:00 akpm@bix.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/26 11:28:15-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/02/26 11:28:09-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/23 20:16:50-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/02/23 20:16:44-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/20 18:41:24-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/02/20 18:41:17-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/20 13:48:13-08:00 akpm@mnm.(none) # Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk # into mnm.(none):/usr/src/bk-arm # # include/asm-arm/pci.h # 2004/02/20 13:48:07-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/20 13:45:54-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # arch/arm/Kconfig # 2004/02/20 13:45:48-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/10 12:08:32-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # include/asm-arm/pci.h # 2004/02/10 12:08:26-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/06 13:18:37-08:00 akpm@mnm.(none) # Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm # # include/asm-arm/pci.h # 2004/02/06 13:18:30-08:00 akpm@mnm.(none) +0 -0 # Auto merged # # ChangeSet # 2004/02/06 10:43:46-08:00 akpm@mnm.(none) # Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk # into mnm.(none):/usr/src/bk-arm # # include/asm-arm/pci.h # 2004/02/06 10:43:40-08:00 akpm@mnm.(none) +0 -0 # Auto merged # diff -Nru a/arch/arm/Kconfig b/arch/arm/Kconfig --- a/arch/arm/Kconfig Sun Apr 4 18:51:05 2004 +++ b/arch/arm/Kconfig Sun Apr 4 18:51:05 2004 @@ -135,6 +135,9 @@ config ARCH_SHARK bool "Shark" +config ARCH_OMAP + bool "TI OMAP" + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -151,6 +154,8 @@ source "arch/arm/mach-sa1100/Kconfig" +source "arch/arm/mach-omap/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -500,7 +505,7 @@ config LEDS bool "Timer and CPU usage LEDs" - depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T + depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -514,7 +519,7 @@ config LEDS_TIMER bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T) - depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T + depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP default y if ARCH_EBSA110 help If you say Y here, one of the system LEDs (the green one on the diff -Nru a/arch/arm/Makefile b/arch/arm/Makefile --- a/arch/arm/Makefile Sun Apr 4 18:51:05 2004 +++ b/arch/arm/Makefile Sun Apr 4 18:51:05 2004 @@ -47,6 +47,7 @@ tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi +tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 @@ -91,6 +92,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx machine-$(CONFIG_ARCH_ADIFCC) := adifcc + machine-$(CONFIG_ARCH_OMAP) := omap TEXTADDR := $(textaddr-y) ifeq ($(incdir-y),) diff -Nru a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile --- a/arch/arm/boot/Makefile Sun Apr 4 18:51:05 2004 +++ b/arch/arm/boot/Makefile Sun Apr 4 18:51:05 2004 @@ -51,6 +51,9 @@ params_phys-$(CONFIG_ARCH_IOP3XX) := 0xa0000100 zreladdr-$(CONFIG_ARCH_ADIFCC) := 0xc0008000 params_phys-$(CONFIG_ARCH_ADIFCC) := 0xc0000100 + zreladdr-$(CONFIG_ARCH_OMAP) := 0x10008000 +params_phys-$(CONFIG_ARCH_OMAP) := 0x10000100 +initrd_phys-$(CONFIG_ARCH_OMAP) := 0x10800000 ZRELADDR := $(zreladdr-y) ZTEXTADDR := $(ztextaddr-y) diff -Nru a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S --- a/arch/arm/kernel/debug.S Sun Apr 4 18:51:05 2004 +++ b/arch/arm/kernel/debug.S Sun Apr 4 18:51:05 2004 @@ -436,6 +436,32 @@ tst \rd, #0x10 beq 1001b .endm + +#elif defined(CONFIG_ARCH_OMAP) + +#include + + .macro addruart,rx + mov \rx, #0xff000000 + orr \rx, \rx, #0x00fb0000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] + .endm + + .macro busyuart,rd,rx +1002: ldrb \rd, [\rx, #(0x5 << OMAP_SERIAL_REG_SHIFT)] + and \rd, \rd, #0x60 + teq \rd, #0x60 + bne 1002b + .endm + + .macro waituart,rd,rx +1001: ldrb \rd, [\rx, #(0x6 << OMAP_SERIAL_REG_SHIFT)] + tst \rd, #0x10 + beq 1001b + .endm #else #error Unknown architecture #endif diff -Nru a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S --- a/arch/arm/kernel/entry-armv.S Sun Apr 4 18:51:05 2004 +++ b/arch/arm/kernel/entry-armv.S Sun Apr 4 18:51:05 2004 @@ -608,6 +608,33 @@ .macro irq_prio_table .endm +#elif defined(CONFIG_ARCH_OMAP) + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) + ldr \irqnr, [\base, #IRQ_ITR] + ldr \tmp, [\base, #IRQ_MIR] + mov \irqstat, #0xffffffff + bic \tmp, \irqstat, \tmp + tst \irqnr, \tmp + beq 1510f + + ldr \irqnr, [\base, #IRQ_SIR_FIQ] + cmp \irqnr, #0 + ldreq \irqnr, [\base, #IRQ_SIR_IRQ] + cmpeq \irqnr, #INT_IH2_IRQ + ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE) + ldreq \irqnr, [\base, #IRQ_SIR_IRQ] + addeqs \irqnr, \irqnr, #32 +1510: + .endm + + .macro irq_prio_table + .endm + #else #error Unknown architecture #endif diff -Nru a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/Kconfig Sun Apr 4 18:51:05 2004 @@ -0,0 +1,113 @@ + +menu "TI OMAP Implementations" + +choice + prompt "OMAP Core Type" + depends on ARCH_OMAP + default ARCH_OMAP1510 + +config ARCH_OMAP1510 + bool "OMAP-1510 Based System" + select CPU_ARM925T + select CPU_DCACHE_WRITETHROUGH + +config ARCH_OMAP1610 + bool "OMAP-1610 Based System" + select CPU_ARM926T + +endchoice + +choice + prompt "OMAP Board Type" + depends on ARCH_OMAP + default MACH_OMAP_INNOVATOR + +config MACH_OMAP_INNOVATOR + bool "TI Innovator" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 + help + TI OMAP 1510 or 1610 Innovator board support. Say Y here if you + have such a board. + +config MACH_OMAP_GENERIC + bool "Generic OMAP board" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 + help + Support for generic OMAP-1510 or 1610 board with no + FPGA. Can be used as template for porting Linux to + custom OMAP boards. Say Y here if you have a custom + board. + +endchoice + +comment "OMAP Feature Selections" + +config MACH_OMAP_H2 + bool "TI H2 Support" + depends on ARCH_OMAP1610 && MACH_OMAP_INNOVATOR + help + TI OMAP 1610 H2 board support. Say Y here if you have such + a board. + +config OMAP_MUX + bool "OMAP multiplexing support" + depends on ARCH_OMAP + default y + help + Pin multiplexing support for OMAP boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. + +config OMAP_MUX_DEBUG + bool "Multiplexing debug output" + depends on OMAP_MUX + default n + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. + +config OMAP_ARM_195MHZ + bool "OMAP ARM 195 MHz CPU" + depends on ARCH_OMAP730 + help + Enable 195MHz clock for OMAP CPU. If unsure, say N. + +config OMAP_ARM_192MHZ + bool "OMAP ARM 192 MHz CPU" + depends on ARCH_OMAP1610 + help + Enable 192MHz clock for OMAP CPU. If unsure, say N. + +config OMAP_ARM_182MHZ + bool "OMAP ARM 182 MHz CPU" + depends on ARCH_OMAP730 + help + Enable 182MHz clock for OMAP CPU. If unsure, say N. + +config OMAP_ARM_168MHZ + bool "OMAP ARM 168 MHz CPU" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 + help + Enable 168MHz clock for OMAP CPU. If unsure, say N. + +config OMAP_ARM_120MHZ + bool "OMAP ARM 120 MHz CPU" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 + help + Enable 120MHz clock for OMAP CPU. If unsure, say N. + +config OMAP_ARM_60MHZ + bool "OMAP ARM 60 MHz CPU" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 + default y + help + Enable 60MHz clock for OMAP CPU. If unsure, say Y. + +config OMAP_ARM_30MHZ + bool "OMAP ARM 30 MHz CPU" + depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 + help + Enable 30MHz clock for OMAP CPU. If unsure, say N. + +endmenu diff -Nru a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/Makefile Sun Apr 4 18:51:05 2004 @@ -0,0 +1,36 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := common.o irq.o dma.o clocks.o mux.o bus.o gpio.o +obj-m := +obj-n := +obj- := +led-y := leds.o + +# OCPI interconnect support for 1610 +ifeq ($(CONFIG_ARCH_OMAP1610),y) +obj-y += ocpi.o +ifeq ($(CONFIG_OMAP_INNOVATOR),y) +obj-y += innovator1610.o +endif +endif + +ifeq ($(CONFIG_ARCH_OMAP1510),y) +ifeq ($(CONFIG_OMAP_INNOVATOR),y) +obj-y += innovator1510.o fpga.o +endif +endif + +# Specific board support +obj-$(CONFIG_MACH_OMAP_GENERIC) += omap-generic.o +obj-$(CONFIG_MACH_OMAP_PERSEUS2) += omap-perseus2.o + +# LEDs support +led-$(CONFIG_OMAP_INNOVATOR) += leds-innovator.o +led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-perseus2.o +obj-$(CONFIG_LEDS) += $(led-y) + +# kgdb support +obj-$(CONFIG_KGDB_SERIAL) += kgdb-serial.o diff -Nru a/arch/arm/mach-omap/bus.c b/arch/arm/mach-omap/bus.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/bus.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,280 @@ +/* + * linux/arch/arm/mach-omap/bus.c + * + * Virtual bus for OMAP. Allows better power management, such as managing + * shared clocks, and mapping of bus addresses to Local Bus addresses. + * + * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for + * examples on how to register drivers to this bus. + * + * Copyright (C) 2003 - 2004 Nokia Corporation + * Written by Tony Lindgren + * Portions of code based on sa1111.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static int omap_bus_match(struct device *_dev, struct device_driver *_drv); +static int omap_bus_suspend(struct device *dev, u32 state); +static int omap_bus_resume(struct device *dev); + +/* + * OMAP bus definitions + * + * NOTE: Most devices should use TIPB. LBUS does automatic address mapping + * to Local Bus addresses, and should only be used for Local Bus devices. + * We may add new buses later on for power management reasons. Basically + * we want to be able to turn off any bus if it's not used by device + * drivers. + */ +static struct device omap_bus_devices[OMAP_NR_BUSES] = { + { + .bus_id = OMAP_BUS_NAME_TIPB + }, { + .bus_id = OMAP_BUS_NAME_LBUS + }, +}; + +static struct bus_type omap_bus_types[OMAP_NR_BUSES] = { + { + .name = OMAP_BUS_NAME_TIPB, + .match = omap_bus_match, + .suspend = omap_bus_suspend, + .resume = omap_bus_resume, + }, { + .name = OMAP_BUS_NAME_LBUS, /* Local bus on 1510 */ + .match = omap_bus_match, + .suspend = omap_bus_suspend, + .resume = omap_bus_resume, + }, +}; + +#ifdef CONFIG_ARCH_OMAP1510 +/* + * NOTE: This code _should_ go somewhere else. But let's wait for the + * dma-mapping code to settle down first. + */ + +/* + * Test for Local Bus device in order to do address translation between + * dma_handle and Local Bus address. + */ +inline int dmadev_uses_omap_lbus(struct device * dev) +{ + return dev->bus == &omap_bus_types[OMAP_BUS_LBUS] ? 1 : 0; +} + +/* + * Translate bus address to Local Bus address for dma-mapping + */ +inline int dmadev_to_lbus(dma_addr_t addr) +{ + return bus_to_lbus(addr); +} + +/* + * Translate Local Bus address to bus address for dma-mapping + */ +inline int lbus_to_dmadev(dma_addr_t addr) +{ + return lbus_to_bus(addr); +} +#endif + +static int omap_bus_match(struct device *dev, struct device_driver *drv) +{ + struct omap_dev *omapdev = OMAP_DEV(dev); + struct omap_driver *omapdrv = OMAP_DRV(drv); + + return omapdev->devid == omapdrv->devid; +} + +static int omap_bus_suspend(struct device *dev, u32 state) +{ + struct omap_dev *omapdev = OMAP_DEV(dev); + struct omap_driver *omapdrv = OMAP_DRV(dev->driver); + int ret = 0; + + if (omapdrv && omapdrv->suspend) + ret = omapdrv->suspend(omapdev, state); + return ret; +} + +static int omap_bus_resume(struct device *dev) +{ + struct omap_dev *omapdev = OMAP_DEV(dev); + struct omap_driver *omapdrv = OMAP_DRV(dev->driver); + int ret = 0; + + if (omapdrv && omapdrv->resume) + ret = omapdrv->resume(omapdev); + return ret; +} + +static int omap_device_probe(struct device *dev) +{ + struct omap_dev *omapdev = OMAP_DEV(dev); + struct omap_driver *omapdrv = OMAP_DRV(dev->driver); + int ret = -ENODEV; + + if (omapdrv && omapdrv->probe) + ret = omapdrv->probe(omapdev); + + return ret; +} + +static int omap_device_remove(struct device *dev) +{ + struct omap_dev *omapdev = OMAP_DEV(dev); + struct omap_driver *omapdrv = OMAP_DRV(dev->driver); + int ret = 0; + + if (omapdrv && omapdrv->remove) + ret = omapdrv->remove(omapdev); + return ret; +} + +int omap_device_register(struct omap_dev *odev) +{ + if (!odev) + return -EINVAL; + + if (odev->busid < 0 || odev->busid >= OMAP_NR_BUSES) { + printk(KERN_ERR "%s: busid invalid: %s: bus: %i\n", + __FUNCTION__, odev->name, odev->busid); + return -EINVAL; + } + + odev->dev.parent = &omap_bus_devices[odev->busid]; + odev->dev.bus = &omap_bus_types[odev->busid]; + + /* This is needed for USB OHCI to work */ + if (odev->dma_mask) + odev->dev.dma_mask = odev->dma_mask; + + snprintf(odev->dev.bus_id, BUS_ID_SIZE, "%s%u", + odev->name, odev->devid); + + printk("Registering OMAP device '%s'. Parent at %s\n", + odev->dev.bus_id, odev->dev.parent->bus_id); + + return device_register(&odev->dev); +} + +void omap_device_unregister(struct omap_dev *odev) +{ + if (odev) + device_unregister(&odev->dev); +} + +int omap_driver_register(struct omap_driver *driver) +{ + int ret; + + if (driver->busid < 0 || driver->busid >= OMAP_NR_BUSES) { + printk(KERN_ERR "%s: busid invalid: bus: %i device: %i\n", + __FUNCTION__, driver->busid, driver->devid); + return -EINVAL; + } + + driver->drv.probe = omap_device_probe; + driver->drv.remove = omap_device_remove; + driver->drv.bus = &omap_bus_types[driver->busid]; + + /* + * driver_register calls bus_add_driver + */ + ret = driver_register(&driver->drv); + + return ret; +} + +void omap_driver_unregister(struct omap_driver *driver) +{ + driver_unregister(&driver->drv); +} + +static int __init omap_bus_init(void) +{ + int i, ret; + + /* Initialize all OMAP virtual buses */ + for (i = 0; i < OMAP_NR_BUSES; i++) { + ret = device_register(&omap_bus_devices[i]); + if (ret != 0) { + printk(KERN_ERR "Unable to register bus device %s\n", + omap_bus_devices[i].bus_id); + continue; + } + ret = bus_register(&omap_bus_types[i]); + if (ret != 0) { + printk(KERN_ERR "Unable to register bus %s\n", + omap_bus_types[i].name); + device_unregister(&omap_bus_devices[i]); + } + } + printk("OMAP virtual buses initialized\n"); + + return ret; +} + +static void __exit omap_bus_exit(void) +{ + int i; + + /* Unregister all OMAP virtual buses */ + for (i = 0; i < OMAP_NR_BUSES; i++) { + bus_unregister(&omap_bus_types[i]); + device_unregister(&omap_bus_devices[i]); + } +} + +module_init(omap_bus_init); +module_exit(omap_bus_exit); + +MODULE_DESCRIPTION("Virtual bus for OMAP"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(omap_bus_types); +EXPORT_SYMBOL(omap_driver_register); +EXPORT_SYMBOL(omap_driver_unregister); +EXPORT_SYMBOL(omap_device_register); +EXPORT_SYMBOL(omap_device_unregister); + +#ifdef CONFIG_ARCH_OMAP1510 +EXPORT_SYMBOL(dmadev_uses_omap_lbus); +EXPORT_SYMBOL(dmadev_to_lbus); +EXPORT_SYMBOL(lbus_to_dmadev); +#endif diff -Nru a/arch/arm/mach-omap/clocks.c b/arch/arm/mach-omap/clocks.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/clocks.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,676 @@ +/* + * Clock interface for OMAP + * + * Copyright (C) 2001 RidgeRun, Inc + * Written by Gordon McNutt + * Updated 2004 for Linux 2.6 by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Input clock in MHz */ +static unsigned int source_clock = 12; + +/* + * We use one spinlock for all clock registers for now. We may want to + * change this to be clock register specific later on. Before we can do + * that, we need to map out the shared clock registers. + */ +static spinlock_t clock_lock = SPIN_LOCK_UNLOCKED; + +typedef struct { + char *name; + __u8 flags; + ck_t parent; + volatile __u16 *rate_reg; /* Clock rate register */ + volatile __u16 *enbl_reg; /* Enable register */ + volatile __u16 *idle_reg; /* Idle register */ + volatile __u16 *slct_reg; /* Select register */ + __s8 rate_shift; /* Clock rate bit shift */ + __s8 enbl_shift; /* Clock enable bit shift */ + __s8 idle_shift; /* Clock idle bit shift */ + __s8 slct_shift; /* Clock select bit shift */ +} ck_info_t; + +#define CK_NAME(ck) ck_info_table[ck].name +#define CK_FLAGS(ck) ck_info_table[ck].flags +#define CK_PARENT(ck) ck_info_table[ck].parent +#define CK_RATE_REG(ck) ck_info_table[ck].rate_reg +#define CK_ENABLE_REG(ck) ck_info_table[ck].enbl_reg +#define CK_IDLE_REG(ck) ck_info_table[ck].idle_reg +#define CK_SELECT_REG(ck) ck_info_table[ck].slct_reg +#define CK_RATE_SHIFT(ck) ck_info_table[ck].rate_shift +#define CK_ENABLE_SHIFT(ck) ck_info_table[ck].enbl_shift +#define CK_IDLE_SHIFT(ck) ck_info_table[ck].idle_shift +#define CK_SELECT_SHIFT(ck) ck_info_table[ck].slct_shift +#define CK_CAN_CHANGE_RATE(cl) (CK_FLAGS(ck) & CK_RATEF) +#define CK_CAN_DISABLE(cl) (CK_FLAGS(ck) & CK_ENABLEF) +#define CK_CAN_IDLE(cl) (CK_FLAGS(ck) & CK_IDLEF) +#define CK_CAN_SWITCH(cl) (CK_FLAGS(ck) & CK_SELECTF) + +static ck_info_t ck_info_table[] = { + { + .name = "clkin", + .flags = 0, + .parent = OMAP_CLKIN, + }, { + .name = "ck_gen1", + .flags = CK_RATEF | CK_IDLEF, + .rate_reg = CK_DPLL1, + .idle_reg = ARM_IDLECT1, + .idle_shift = IDLDPLL_ARM, + .parent = OMAP_CLKIN, + }, { + .name = "ck_gen2", + .flags = 0, + .parent = OMAP_CK_GEN1, + }, { + .name = "ck_gen3", + .flags = 0, + .parent = OMAP_CK_GEN1, + }, { + .name = "tc_ck", + .flags = CK_RATEF | CK_IDLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .idle_reg = ARM_IDLECT1, + .rate_shift = TCDIV, + .idle_shift = IDLIF_ARM + }, { + .name = "arm_ck", + .flags = CK_IDLEF | CK_RATEF, + .parent = OMAP_CK_GEN1, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[ARMDIV(5:4)] */ + .idle_reg = ARM_IDLECT1, + .rate_shift = ARMDIV, + .idle_shift = SETARM_IDLE, + }, { + .name = "mpuper_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN1, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[PERDIV(1:0)] */ + .enbl_reg = ARM_IDLECT2, + .idle_reg = ARM_IDLECT1, + .rate_shift = PERDIV, + .enbl_shift = EN_PERCK, + .idle_shift = IDLPER_ARM + }, { + .name = "arm_gpio_ck", + .flags = CK_ENABLEF, + .parent = OMAP_CK_GEN1, + .enbl_reg = ARM_IDLECT2, + .enbl_shift = EN_GPIOCK + }, { + .name = "mpuxor_ck", + .flags = CK_ENABLEF | CK_IDLEF, + .parent = OMAP_CLKIN, + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .idle_shift = IDLXORP_ARM, + .enbl_shift = EN_XORPCK + }, { + .name = "mputim_ck", + .flags = CK_IDLEF | CK_ENABLEF | CK_SELECTF, + .parent = OMAP_CLKIN, + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .slct_reg = ARM_CKCTL, + .idle_shift = IDLTIM_ARM, + .enbl_shift = EN_TIMCK, + .slct_shift = ARM_TIMXO + }, { + .name = "mpuwd_ck", + .flags = CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CLKIN, + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .idle_shift = IDLWDT_ARM, + .enbl_shift = EN_WDTCK, + }, { + .name = "dsp_ck", + .flags = CK_RATEF | CK_ENABLEF, + .parent = OMAP_CK_GEN2, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[DSPDIV(7:6)] */ + .enbl_reg = ARM_CKCTL, + .rate_shift = DSPDIV, + .enbl_shift = EN_DSPCK, + }, { + .name = "dspmmu_ck", + .flags = CK_RATEF | CK_ENABLEF, + .parent = OMAP_CK_GEN2, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[DSPMMUDIV(11:10)] */ + .enbl_reg = ARM_CKCTL, + .rate_shift = DSPMMUDIV, + .enbl_shift = EN_DSPCK, + }, { + .name = "dma_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .rate_shift = TCDIV, + .idle_shift = IDLIF_ARM, + .enbl_shift = DMACK_REQ + }, { + .name = "api_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .rate_shift = TCDIV, + .idle_shift = IDLAPI_ARM, + .enbl_shift = EN_APICK, + }, { + .name = "hsab_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .rate_shift = TCDIV, + .idle_shift = IDLHSAB_ARM, + .enbl_shift = EN_HSABCK, + }, { + .name = "lbfree_ck", + .flags = CK_RATEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .enbl_reg = ARM_IDLECT2, + .rate_shift = TCDIV, + .enbl_shift = EN_LBFREECK, + }, { + .name = "lb_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[TCDIV(9:8)] */ + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .rate_shift = TCDIV, + .idle_shift = IDLLB_ARM, + .enbl_shift = EN_LBCK, + }, { + .name = "lcd_ck", + .flags = CK_RATEF | CK_IDLEF | CK_ENABLEF, + .parent = OMAP_CK_GEN3, + .rate_reg = ARM_CKCTL, /* ARM_CKCTL[LCDDIV(3:2)] */ + .idle_reg = ARM_IDLECT1, + .enbl_reg = ARM_IDLECT2, + .rate_shift = LCDDIV, + .idle_shift = IDLLCD_ARM, + .enbl_shift = EN_LCDCK, + }, +}; + +/*****************************************************************************/ + +#define CK_IN_RANGE(ck) (!((ck < OMAP_CK_MIN) || (ck > OMAP_CK_MAX))) + +int ck_auto_unclock = 1; +int ck_debug = 0; + +#define CK_MAX_PLL_FREQ OMAP_CK_MAX_RATE +static __u8 ck_valid_table[CK_MAX_PLL_FREQ / 8 + 1]; +static __u8 ck_lookup_table[CK_MAX_PLL_FREQ]; + +int +ck_set_input(ck_t ck, ck_t input) +{ + int ret = 0, shift; + volatile __u16 *reg; + unsigned long flags; + + if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) { + ret = -EINVAL; + goto exit; + } + + reg = CK_SELECT_REG(ck); + shift = CK_SELECT_SHIFT(ck); + + spin_lock_irqsave(&clock_lock, flags); + if (input == OMAP_CLKIN) { + *((volatile __u16 *) reg) &= ~(1 << shift); + goto exit; + } else if (input == CK_PARENT(ck)) { + *((volatile __u16 *) reg) |= (1 << shift); + goto exit; + } + + ret = -EINVAL; + exit: + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} + +int +ck_get_input(ck_t ck, ck_t * input) +{ + int ret = -EINVAL; + unsigned long flags; + + if (!CK_IN_RANGE(ck)) + goto exit; + + ret = 0; + + spin_lock_irqsave(&clock_lock, flags); + if (CK_CAN_SWITCH(ck)) { + int shift; + volatile __u16 *reg; + + reg = CK_SELECT_REG(ck); + shift = CK_SELECT_SHIFT(ck); + if (*reg & (1 << shift)) { + *input = CK_PARENT(ck); + goto exit; + } + } + + *input = OMAP_CLKIN; + + exit: + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} + +static int +__ck_set_pll_rate(ck_t ck, int rate) +{ + volatile __u16 *pll; + unsigned long flags; + + if ((rate < 0) || (rate > CK_MAX_PLL_FREQ)) + return -EINVAL; + + /* Scan downward for the closest matching frequency */ + while (rate && !test_bit(rate, (unsigned long *)&ck_valid_table)) + rate--; + + if (!rate) { + printk(KERN_ERR "%s: couldn't find a matching rate\n", + __FUNCTION__); + return -EINVAL; + } + + spin_lock_irqsave(&clock_lock, flags); + pll = (volatile __u16 *) CK_RATE_REG(ck); + + /* Clear the rate bits */ + *pll &= ~(0x1f << 5); + + /* Set the rate bits */ + *pll |= (ck_lookup_table[rate - 1] << 5); + spin_unlock_irqrestore(&clock_lock, flags); + + return 0; +} + +static int +__ck_set_clkm_rate(ck_t ck, int rate) +{ + int shift, prate, div, ret; + volatile __u16 *reg; + unsigned long flags; + + spin_lock_irqsave(&clock_lock, flags); + + /* + * We can only set this clock's value to a fraction of its + * parent's value. The interface says I'll round down when necessary. + * So first let's get the parent's current rate. + */ + prate = ck_get_rate(CK_PARENT(ck)); + + /* + * Let's just start with the highest fraction and keep searching + * down through available rates until we find one less than or equal + * to the desired rate. + */ + for (div = 0; div < 4; div++) { + if (prate <= rate) + break; + prate = prate / 2; + } + + /* + * Oops. Looks like the caller wants a rate lower than we can support. + */ + if (div == 5) { + printk(KERN_ERR "%s: %d is too low\n", + __FUNCTION__, rate); + ret = -EINVAL; + goto exit; + } + + /* + * One more detail: if this clock supports more than one parent, then + * we're going to automatically switch over to the parent which runs + * through the divisor. For omap this is not ambiguous because for all + * such clocks one choice is always OMAP_CLKIN (which doesn't run + * through the divisor) and the other is whatever I encoded as + * CK_PARENT. Note that I wait until we get this far because I don't + * want to switch the input until we're sure this is going to work. + */ + if (CK_CAN_SWITCH(ck)) + if ((ret = ck_set_input(ck, CK_PARENT(ck))) < 0) { + BUG(); + goto exit; + } + + /* + * At last, we can set the divisor. Clear the old rate bits and + * set the new ones. + */ + reg = (volatile __u16 *) CK_RATE_REG(ck); + shift = CK_RATE_SHIFT(ck); + *reg &= ~(3 << shift); + *reg |= (div << shift); + + /* And return the new (actual, after rounding down) rate. */ + ret = prate; + + exit: + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} + +int +ck_set_rate(ck_t ck, int rate) +{ + int ret = -EINVAL; + + if (!CK_IN_RANGE(ck) || !CK_CAN_CHANGE_RATE(ck)) + goto exit; + + switch (ck) { + + default: + ret = __ck_set_clkm_rate(ck, rate); + break; + + case OMAP_CK_GEN1: + ret = __ck_set_pll_rate(ck, rate); + break; + + }; + + exit: + return ret; +} + +static int +__ck_get_pll_rate(ck_t ck) +{ + int m, d; + + __u16 pll = *((volatile __u16 *) CK_RATE_REG(ck)); + + m = (pll & (0x1f << 7)) >> 7; + m = m ? m : 1; + d = (pll & (3 << 5)) >> 5; + d++; + + return ((source_clock * m) / d); +} + +static int +__ck_get_clkm_rate(ck_t ck) +{ + static int bits2div[] = { 1, 2, 4, 8 }; + int in, bits, reg, shift; + + reg = *(CK_RATE_REG(ck)); + shift = CK_RATE_SHIFT(ck); + + in = ck_get_rate(CK_PARENT(ck)); + bits = (reg & (3 << shift)) >> shift; + + return (in / bits2div[bits]); +} + +int +ck_get_rate(ck_t ck) +{ + int ret = 0; + ck_t parent; + + if (!CK_IN_RANGE(ck)) { + ret = -EINVAL; + goto exit; + } + + switch (ck) { + + case OMAP_CK_GEN1: + ret = __ck_get_pll_rate(ck); + break; + + case OMAP_CLKIN: + ret = source_clock; + break; + + case OMAP_MPUXOR_CK: + case OMAP_CK_GEN2: + case OMAP_CK_GEN3: + case OMAP_ARM_GPIO_CK: + ret = ck_get_rate(CK_PARENT(ck)); + break; + + case OMAP_ARM_CK: + case OMAP_MPUPER_CK: + case OMAP_DSP_CK: + case OMAP_DSPMMU_CK: + case OMAP_LCD_CK: + case OMAP_TC_CK: + case OMAP_DMA_CK: + case OMAP_API_CK: + case OMAP_HSAB_CK: + case OMAP_LBFREE_CK: + case OMAP_LB_CK: + ret = __ck_get_clkm_rate(ck); + break; + + case OMAP_MPUTIM_CK: + ck_get_input(ck, &parent); + ret = ck_get_rate(parent); + break; + + case OMAP_MPUWD_CK: + /* Note that this evaluates to zero if source_clock is 12MHz. */ + ret = source_clock / 14; + break; + default: + ret = -EINVAL; + break; + } + + exit: + return ret; +} + +int +ck_enable(ck_t ck) +{ + volatile __u16 *reg; + int ret = -EINVAL, shift; + unsigned long flags; + + if (!CK_IN_RANGE(ck)) + goto exit; + + if (ck_debug) + printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck)); + + ret = 0; + + if (!CK_CAN_DISABLE(ck)) + /* Then it must be on... */ + goto exit; + + spin_lock_irqsave(&clock_lock, flags); + reg = CK_ENABLE_REG(ck); + shift = CK_ENABLE_SHIFT(ck); + *reg |= (1 << shift); + spin_unlock_irqrestore(&clock_lock, flags); + + exit: + return ret; +} + +int +ck_disable(ck_t ck) +{ + volatile __u16 *reg; + int ret = -EINVAL, shift; + unsigned long flags; + + if (!CK_IN_RANGE(ck)) + goto exit; + + if (ck_debug) + printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck)); + + if (!CK_CAN_DISABLE(ck)) + goto exit; + + ret = 0; + + if (ck == OMAP_CLKIN) + return -EINVAL; + + spin_lock_irqsave(&clock_lock, flags); + reg = CK_ENABLE_REG(ck); + shift = CK_ENABLE_SHIFT(ck); + *reg &= ~(1 << shift); + spin_unlock_irqrestore(&clock_lock, flags); + + exit: + return ret; +} + +int ck_valid_rate(int rate) +{ + return test_bit(rate, (unsigned long *)&ck_valid_table); +} + +static void +__ck_make_lookup_table(void) +{ + __u8 m, d; + + memset(ck_valid_table, 0, sizeof (ck_valid_table)); + + for (m = 1; m < 32; m++) + for (d = 1; d < 5; d++) { + + int rate = ((source_clock * m) / (d)); + + if (rate > CK_MAX_PLL_FREQ) + continue; + if (test_bit(rate, (unsigned long *)&ck_valid_table)) + continue; + set_bit(rate, (unsigned long *)&ck_valid_table); + ck_lookup_table[rate - 1] = (m << 2) | (d - 1); + } +} + +int __init +init_ck(void) +{ + __ck_make_lookup_table(); + + /* We want to be in syncronous scalable mode */ + *ARM_SYSST = 0x1000; +#if defined(CONFIG_OMAP_ARM_30MHZ) + *ARM_CKCTL = 0x1555; + *DPLL_CTL_REG = 0x2290; +#elif defined(CONFIG_OMAP_ARM_60MHZ) + *ARM_CKCTL = 0x1005; + *DPLL_CTL_REG = 0x2290; +#elif defined(CONFIG_OMAP_ARM_96MHZ) + *ARM_CKCTL = 0x1005; + *DPLL_CTL_REG = 0x2410; +#elif defined(CONFIG_OMAP_ARM_120MHZ) + *ARM_CKCTL = 0x110a; + *DPLL_CTL_REG = 0x2510; +#elif defined(CONFIG_OMAP_ARM_168MHZ) + *ARM_CKCTL = 0x110f; + *DPLL_CTL_REG = 0x2710; +#elif defined(CONFIG_OMAP_ARM_182MHZ) && defined(CONFIG_ARCH_OMAP730) + *ARM_CKCTL = 0x250E; + *DPLL_CTL_REG = 0x2713; +#elif defined(CONFIG_OMAP_ARM_192MHZ) && defined(CONFIG_ARCH_OMAP1610) + *ARM_CKCTL = 0x110f; + if (crystal_type == 2) { + source_clock = 13; /* MHz */ + *DPLL_CTL_REG = 0x2510; + } else + *DPLL_CTL_REG = 0x2810; +#elif defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730) + *ARM_CKCTL = 0x250E; + *DPLL_CTL_REG = 0x2793; +#else +#error "OMAP MHZ not set, please run make xconfig" +#endif + + /* Turn off some other junk the bootloader might have turned on */ + *ARM_CKCTL &= 0x0fff; /* Turn off DSP, ARM_INTHCK, ARM_TIMXO */ + *ARM_RSTCT1 = 0; /* Put DSP/MPUI into reset until needed */ + *ARM_RSTCT2 = 1; + *ARM_IDLECT1 = 0x400; + + /* + * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) + * of the ARM_IDLECT2 register must be set to zero. The power-on + * default value of this bit is one. + */ + *ARM_IDLECT2 = 0x0000; /* Turn LCD clock off also */ + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + ck_enable(OMAP_MPUPER_CK); + ck_enable(OMAP_ARM_GPIO_CK); + ck_enable(OMAP_MPUXOR_CK); + //ck_set_rate(OMAP_MPUTIM_CK, OMAP_CLKIN); + ck_enable(OMAP_MPUTIM_CK); + start_mputimer1(0xffffffff); + + return 0; +} + + +EXPORT_SYMBOL(ck_get_rate); +EXPORT_SYMBOL(ck_set_rate); +EXPORT_SYMBOL(ck_enable); +EXPORT_SYMBOL(ck_disable); diff -Nru a/arch/arm/mach-omap/common.c b/arch/arm/mach-omap/common.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/common.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,69 @@ +/* + * linux/arch/arm/mach-omap/common.c + * + * Code common to all OMAP machines. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "common.h" + +/* + * Common OMAP I/O mapping + * + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. + */ + +static struct map_desc standard_io_desc[] __initdata = { + { IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, + { OMAP_DSP_BASE, OMAP_DSP_START, OMAP_DSP_SIZE, MT_DEVICE }, + { OMAP_DSPREG_BASE, OMAP_DSPREG_START, OMAP_DSPREG_SIZE, MT_DEVICE }, + { OMAP_SRAM_BASE, OMAP_SRAM_START, OMAP_SRAM_SIZE, MT_DEVICE } +}; + +static int initialized = 0; + +static void __init _omap_map_io(void) +{ + initialized = 1; + + iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); + + /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort + * on a Posted Write in the TIPB Bridge". + */ + __raw_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG); + __raw_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG); + + /* Must init clocks early to assure that timer interrupt works + */ + init_ck(); +} + +/* + * This should only get called from board specific init + */ +void omap_map_io(void) +{ + if (!initialized) + _omap_map_io(); +} + +EXPORT_SYMBOL(omap_map_io); + diff -Nru a/arch/arm/mach-omap/common.h b/arch/arm/mach-omap/common.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/common.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,6 @@ +/* + * linux/arch/arm/mach-omap/common.h + */ + +extern void omap_map_io(void); + diff -Nru a/arch/arm/mach-omap/dma.c b/arch/arm/mach-omap/dma.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/dma.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,560 @@ +/* + * linux/arch/arm/omap/dma.c + * + * Copyright (C) 2003 Nokia Corporation + * Author: Juha Yrjölä + * + * Support functions for the OMAP internal DMA channels. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define OMAP_DMA_ACTIVE 0x01 + +#define OMAP_DMA_CCR_EN (1 << 7) + +#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) + +static int enable_1510_mode = 0; + +struct omap_dma_lch { + int dev_id; + u16 saved_csr; + u16 enabled_irqs; + const char *dev_name; + void (* callback)(int lch, u16 ch_status, void *data); + void *data; + long flags; +}; + +static int dma_chan_count; + +static spinlock_t dma_chan_lock; +static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; + +const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { + INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, + INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, + INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, + INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, + INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD +}; + +static inline int get_gdma_dev(int req) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + + return ((__raw_readl(reg) >> shift) & 0x3f) + 1; +} + +static inline void set_gdma_dev(int req, int dev) +{ + u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; + int shift = ((req - 1) % 5) * 6; + u32 l; + + l = __raw_readl(reg); + l &= ~(0x3f << shift); + l |= (dev - 1) << shift; + __raw_writel(l, reg); +} + +static void clear_lch_regs(int lch) +{ + int i; + u32 lch_base = OMAP_DMA_BASE + lch * 0x40; + + for (i = 0; i < 0x2c; i += 2) + __raw_writew(0, lch_base + i); +} + +void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, + int frame_count, int sync_mode) +{ + u16 w; + + w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w &= ~0x03; + w |= data_type; + __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w &= ~(1 << 5); + if (sync_mode == OMAP_DMA_SYNC_FRAME) + w |= 1 << 5; + __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR2_REG(lch)); + w &= ~(1 << 2); + if (sync_mode == OMAP_DMA_SYNC_BLOCK) + w |= 1 << 2; + __raw_writew(w, OMAP_DMA_CCR2_REG(lch)); + + __raw_writew(elem_count, OMAP_DMA_CEN_REG(lch)); + __raw_writew(frame_count, OMAP_DMA_CFN_REG(lch)); + +} + +void omap_set_dma_src_params(int lch, int src_port, int src_amode, + unsigned long src_start) +{ + u16 w; + + w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w &= ~(0x1f << 2); + w |= src_port << 2; + __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w &= ~(0x03 << 12); + w |= src_amode << 12; + __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + + __raw_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch)); + __raw_writew(src_start, OMAP_DMA_CSSA_L_REG(lch)); +} + +void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, + unsigned long dest_start) +{ + u16 w; + + w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w &= ~(0x1f << 9); + w |= dest_port << 9; + __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w &= ~(0x03 << 14); + w |= dest_amode << 14; + __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + + __raw_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch)); + __raw_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch)); +} + +void omap_start_dma(int lch) +{ + u16 w; + + /* Read CSR to make sure it's cleared. */ + w = __raw_readw(OMAP_DMA_CSR_REG(lch)); + /* Enable some nice interrupts. */ + __raw_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w |= OMAP_DMA_CCR_EN; + __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + dma_chan[lch].flags |= OMAP_DMA_ACTIVE; +} + +void omap_stop_dma(int lch) +{ + u16 w; + + /* Disable all interrupts on the channel */ + __raw_writew(0, OMAP_DMA_CICR_REG(lch)); + + w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w &= ~OMAP_DMA_CCR_EN; + __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; +} + +void omap_enable_dma_irq(int lch, u16 bits) +{ + dma_chan[lch].enabled_irqs |= bits; +} + +void omap_disable_dma_irq(int lch, u16 bits) +{ + dma_chan[lch].enabled_irqs &= ~bits; +} + +static int dma_handle_ch(int ch) +{ + u16 csr; + + if (enable_1510_mode && ch >= 6) { + csr = dma_chan[ch].saved_csr; + dma_chan[ch].saved_csr = 0; + } else + csr = __raw_readw(OMAP_DMA_CSR_REG(ch)); + if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { + dma_chan[ch + 6].saved_csr = csr >> 7; + csr &= 0x7f; + } + if (!csr) + return 0; + if (unlikely(dma_chan[ch].dev_id == -1)) { + printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n", + ch, csr); + return 0; + } + if (unlikely(csr & OMAP_DMA_TOUT_IRQ)) + printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id); + if (unlikely(csr & OMAP_DMA_DROP_IRQ)) + printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); + if (likely(csr & OMAP_DMA_BLOCK_IRQ)) + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + if (likely(dma_chan[ch].callback != NULL)) + dma_chan[ch].callback(ch, csr, dma_chan[ch].data); + return 1; +} + +static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) +{ + int ch = ((int) dev_id) - 1; + int handled = 0; + + for (;;) { + int handled_now = 0; + + handled_now += dma_handle_ch(ch); + if (enable_1510_mode && dma_chan[ch + 6].saved_csr) + handled_now += dma_handle_ch(ch + 6); + if (!handled_now) + break; + handled += handled_now; + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +int omap_request_dma(int dev_id, const char *dev_name, + void (* callback)(int lch, u16 ch_status, void *data), + void *data, int *dma_ch_out) +{ + int ch, free_ch = -1; + unsigned long flags; + struct omap_dma_lch *chan; + + spin_lock_irqsave(&dma_chan_lock, flags); + for (ch = 0; ch < dma_chan_count; ch++) { + if (free_ch == -1 && dma_chan[ch].dev_id == -1) { + free_ch = ch; + if (dev_id == 0) + break; + } + if (dev_id != 0 && dma_chan[ch].dev_id == dev_id) { + spin_unlock_irqrestore(&dma_chan_lock, flags); + return -EAGAIN; + } + } + if (free_ch == -1) { + spin_unlock_irqrestore(&dma_chan_lock, flags); + return -EBUSY; + } + chan = dma_chan + free_ch; + chan->dev_id = dev_id; + clear_lch_regs(free_ch); + spin_unlock_irqrestore(&dma_chan_lock, flags); + + chan->dev_id = dev_id; + chan->dev_name = dev_name; + chan->callback = callback; + chan->data = data; + chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; + + if (cpu_is_omap1610()) { + /* If the sync device is set, configure it dynamically. */ + if (dev_id != 0) { + set_gdma_dev(free_ch + 1, dev_id); + dev_id = free_ch + 1; + } + /* Disable the 1510 compatibility mode and set the sync device + * id. */ + __raw_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch)); + } else { + __raw_writew(dev_id, OMAP_DMA_CCR_REG(free_ch)); + } + *dma_ch_out = free_ch; + + return 0; +} + +void omap_free_dma(int ch) +{ + unsigned long flags; + + spin_lock_irqsave(&dma_chan_lock, flags); + if (dma_chan[ch].dev_id == -1) { + printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch); + spin_unlock_irqrestore(&dma_chan_lock, flags); + return; + } + dma_chan[ch].dev_id = -1; + spin_unlock_irqrestore(&dma_chan_lock, flags); + + /* Disable all DMA interrupts for the channel. */ + __raw_writew(0, OMAP_DMA_CICR_REG(ch)); + /* Make sure the DMA transfer is stopped. */ + __raw_writew(0, OMAP_DMA_CCR_REG(ch)); +} + +int omap_dma_in_1510_mode(void) +{ + return enable_1510_mode; +} + + +static struct lcd_dma_info { + spinlock_t lock; + int reserved; + void (* callback)(u16 status, void *data); + void *cb_data; + + unsigned long addr, size; + int rotate, data_type, xres, yres; +} lcd_dma; + +void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, + int data_type) +{ + lcd_dma.addr = addr; + lcd_dma.data_type = data_type; + lcd_dma.xres = fb_xres; + lcd_dma.yres = fb_yres; +} + +static void set_b1_regs(void) +{ + unsigned long top, bottom; + int es; + u16 w, en, fn; + s16 ei; + s32 fi; + u32 l; + + switch (lcd_dma.data_type) { + case OMAP_DMA_DATA_TYPE_S8: + es = 1; + break; + case OMAP_DMA_DATA_TYPE_S16: + es = 2; + break; + case OMAP_DMA_DATA_TYPE_S32: + es = 4; + break; + default: + BUG(); + return; + } + + if (lcd_dma.rotate == 0) { + top = lcd_dma.addr; + bottom = lcd_dma.addr + (lcd_dma.xres * lcd_dma.yres - 1) * es; + /* 1510 DMA requires the bottom address to be 2 more than the + * actual last memory access location. */ + if (omap_dma_in_1510_mode() && + lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) + bottom += 2; + en = lcd_dma.xres; + fn = lcd_dma.yres; + ei = 0; + fi = 0; + } else { + top = lcd_dma.addr + (lcd_dma.xres - 1) * es; + bottom = lcd_dma.addr + (lcd_dma.yres - 1) * lcd_dma.xres * es; + en = lcd_dma.yres; + fn = lcd_dma.xres; + ei = (lcd_dma.xres - 1) * es + 1; + fi = -(lcd_dma.xres * (lcd_dma.yres - 1) + 2) * 2 + 1; + } + + if (omap_dma_in_1510_mode()) { + __raw_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); + __raw_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); + __raw_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); + __raw_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); + + return; + } + + /* 1610 regs */ + __raw_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); + __raw_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); + __raw_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); + __raw_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); + + __raw_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); + __raw_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); + + w = __raw_readw(OMAP1610_DMA_LCD_CSDP); + w &= ~0x03; + w |= lcd_dma.data_type; + __raw_writew(w, OMAP1610_DMA_LCD_CSDP); + + if (!lcd_dma.rotate) + return; + + /* Rotation stuff */ + l = __raw_readw(OMAP1610_DMA_LCD_CSDP); + /* Disable burst access */ + l &= ~(0x03 << 7); + __raw_writew(l, OMAP1610_DMA_LCD_CSDP); + + l = __raw_readw(OMAP1610_DMA_LCD_CCR); + /* Set the double-indexed addressing mode */ + l |= (0x03 << 12); + __raw_writew(l, OMAP1610_DMA_LCD_CCR); + + __raw_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); + __raw_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); + __raw_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); +} + +void omap_set_lcd_dma_b1_rotation(int rotate) +{ + if (omap_dma_in_1510_mode()) { + printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); + BUG(); + return; + } + lcd_dma.rotate = rotate; +} + +int omap_request_lcd_dma(void (* callback)(u16 status, void *data), + void *data) +{ + spin_lock_irq(&lcd_dma.lock); + if (lcd_dma.reserved) { + spin_unlock_irq(&lcd_dma.lock); + printk(KERN_ERR "LCD DMA channel already reserved\n"); + BUG(); + return -EBUSY; + } + lcd_dma.reserved = 1; + spin_unlock_irq(&lcd_dma.lock); + lcd_dma.callback = callback; + lcd_dma.cb_data = data; + + return 0; +} + +void omap_free_lcd_dma(void) +{ + spin_lock(&lcd_dma.lock); + if (!lcd_dma.reserved) { + spin_unlock(&lcd_dma.lock); + printk(KERN_ERR "LCD DMA is not reserved\n"); + BUG(); + return; + } + if (!enable_1510_mode) + __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); + lcd_dma.reserved = 0; + spin_unlock(&lcd_dma.lock); +} + +void omap_start_lcd_dma(void) +{ + if (!enable_1510_mode) { + /* Set some reasonable defaults */ + __raw_writew(0x9102, OMAP1610_DMA_LCD_CSDP); + __raw_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); + __raw_writew(0x5740, OMAP1610_DMA_LCD_CCR); + } + set_b1_regs(); + if (!enable_1510_mode) + __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR); +} + +void omap_stop_lcd_dma(void) +{ + if (!enable_1510_mode) + __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); +} + +static int __init omap_init_dma(void) +{ + int ch, r; + + if (cpu_is_omap1510()) { + printk(KERN_INFO "DMA support for OMAP1510 initialized\n"); + dma_chan_count = 9; + enable_1510_mode = 1; + } else if (cpu_is_omap1610()) { + printk(KERN_INFO "OMAP DMA hardware version %d\n", + __raw_readw(OMAP_DMA_HW_ID_REG)); + printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", + (__raw_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_0_L_REG), + (__raw_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_1_L_REG), + __raw_readw(OMAP_DMA_CAPS_2_REG), __raw_readw(OMAP_DMA_CAPS_3_REG), + __raw_readw(OMAP_DMA_CAPS_4_REG)); + if (!enable_1510_mode) { + u16 w; + + /* Disable OMAP 3.0/3.1 compatibility mode. */ + w = __raw_readw(OMAP_DMA_GSCR_REG); + w |= 1 << 3; + __raw_writew(w, OMAP_DMA_GSCR_REG); + dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; + } else + dma_chan_count = 9; + } else { + dma_chan_count = 0; + return 0; + } + + memset(&lcd_dma, 0, sizeof(lcd_dma)); + spin_lock_init(&lcd_dma.lock); + spin_lock_init(&dma_chan_lock); + memset(&dma_chan, 0, sizeof(dma_chan)); + + for (ch = 0; ch < dma_chan_count; ch++) { + dma_chan[ch].dev_id = -1; + if (ch >= 6 && enable_1510_mode) + continue; + + /* request_irq() doesn't like dev_id (ie. ch) being zero, + * so we have to kludge around this. */ + r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA", + (void *) (ch + 1)); + if (r != 0) { + int i; + + printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n", + dma_irq[ch], r); + for (i = 0; i < ch; i++) + free_irq(dma_irq[i], (void *) (i + 1)); + return r; + } + } + + return 0; +} +arch_initcall(omap_init_dma); + +EXPORT_SYMBOL(omap_request_dma); +EXPORT_SYMBOL(omap_free_dma); +EXPORT_SYMBOL(omap_start_dma); +EXPORT_SYMBOL(omap_stop_dma); +EXPORT_SYMBOL(omap_set_dma_transfer_params); +EXPORT_SYMBOL(omap_set_dma_src_params); +EXPORT_SYMBOL(omap_set_dma_dest_params); + +EXPORT_SYMBOL(omap_request_lcd_dma); +EXPORT_SYMBOL(omap_free_lcd_dma); +EXPORT_SYMBOL(omap_start_lcd_dma); +EXPORT_SYMBOL(omap_stop_lcd_dma); +EXPORT_SYMBOL(omap_set_lcd_dma_b1); +EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); diff -Nru a/arch/arm/mach-omap/fpga.c b/arch/arm/mach-omap/fpga.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/fpga.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,209 @@ +/* + * linux/arch/arm/mach-omap/fpga.c + * + * Interrupt handler for OMAP-1510 FPGA + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +unsigned char fpga_read(int reg) +{ + return __raw_readb(reg); +} + +void fpga_write(unsigned char val, int reg) +{ + __raw_writeb(val, reg); +} + +static void fpga_mask_irq(unsigned int irq) +{ + irq -= IH_FPGA_BASE; + + if (irq < 8) + __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO) + & ~(1 << irq)), OMAP1510P1_FPGA_IMR_LO); + else if (irq < 16) + __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI) + & ~(1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI); + else + __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) + & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2); +} + + +static inline u32 get_fpga_unmasked_irqs(void) +{ + return + ((__raw_readb(OMAP1510P1_FPGA_ISR_LO) & + __raw_readb(OMAP1510P1_FPGA_IMR_LO))) | + ((__raw_readb(OMAP1510P1_FPGA_ISR_HI) & + __raw_readb(OMAP1510P1_FPGA_IMR_HI)) << 8) | + ((__raw_readb(INNOVATOR_FPGA_ISR2) & + __raw_readb(INNOVATOR_FPGA_IMR2)) << 16); +} + + +static void fpga_ack_irq(unsigned int irq) +{ + /* Don't need to explicitly ACK FPGA interrupts */ +} + +static void fpga_unmask_irq(unsigned int irq) +{ + irq -= IH_FPGA_BASE; + + if (irq < 8) + __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO) | (1 << irq)), + OMAP1510P1_FPGA_IMR_LO); + else if (irq < 16) + __raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI) + | (1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI); + else + __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) + | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); +} + +static void fpga_mask_ack_irq(unsigned int irq) +{ + fpga_mask_irq(irq); + fpga_ack_irq(irq); +} + +void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + struct irqdesc *d; + u32 stat; + int fpga_irq; + + /* + * Acknowledge the parent IRQ. + */ + desc->chip->ack(irq); + + for (;;) { + stat = get_fpga_unmasked_irqs(); + + if (!stat) { + break; + } + + for (fpga_irq = IH_FPGA_BASE; + (fpga_irq < (IH_FPGA_BASE + NR_FPGA_IRQS)) && stat; + fpga_irq++, stat >>= 1) { + if (stat & 1) { + d = irq_desc + fpga_irq; + d->handle(fpga_irq, d, regs); + desc->chip->unmask(irq); + } + } + } +} + +static struct irqchip omap_fpga_irq_ack = { + .ack = fpga_mask_ack_irq, + .mask = fpga_mask_irq, + .unmask = fpga_unmask_irq, +}; + + +static struct irqchip omap_fpga_irq = { + .ack = fpga_ack_irq, + .mask = fpga_mask_irq, + .unmask = fpga_unmask_irq, +}; + +/* + * All of the FPGA interrupt request inputs except for the touchscreen are + * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive + * interrupts are acknowledged as a side-effect of reading the interrupt + * status register from the FPGA. The edge-sensitive interrupt inputs + * cause a problem with level interrupt requests, such as Ethernet. The + * problem occurs when a level interrupt request is asserted while its + * interrupt input is masked in the FPGA, which results in a missed + * interrupt. + * + * In an attempt to workaround the problem with missed interrupts, the + * mask_ack routine for all of the FPGA interrupts has been changed from + * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt + * being serviced is left unmasked. We can do this because the FPGA cascade + * interrupt is installed with the SA_INTERRUPT flag, which leaves all + * interrupts masked at the CPU while an FPGA interrupt handler executes. + * + * Limited testing indicates that this workaround appears to be effective + * for the smc9194 Ethernet driver used on the Innovator. It should work + * on other FPGA interrupts as well, but any drivers that explicitly mask + * interrupts at the interrupt controller via disable_irq/enable_irq + * could pose a problem. + */ +void fpga_init_irq(void) +{ + int i; + + __raw_writeb(0, OMAP1510P1_FPGA_IMR_LO); + __raw_writeb(0, OMAP1510P1_FPGA_IMR_HI); + __raw_writeb(0, INNOVATOR_FPGA_IMR2); + + for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + NR_FPGA_IRQS); i++) { + + if (i == INT_FPGA_TS) { + /* + * The touchscreen interrupt is level-sensitive, so + * we'll use the regular mask_ack routine for it. + */ + set_irq_chip(i, &omap_fpga_irq_ack); + } + else { + /* + * All FPGA interrupts except the touchscreen are + * edge-sensitive, so we won't mask them. + */ + set_irq_chip(i, &omap_fpga_irq); + } + + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID); + } + + /* + * The FPGA interrupt line is connected to GPIO13. Claim this pin for + * the ARM. + * + * NOTE: For general GPIO/MPUIO access and interrupts, please see + * gpio.[ch] + */ + omap_request_gpio(13); + omap_set_gpio_direction(13, 1); + omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE); + set_irq_chained_handler(INT_FPGA, innovator_fpga_IRQ_demux); +} + +EXPORT_SYMBOL(fpga_init_irq); +EXPORT_SYMBOL(fpga_read); +EXPORT_SYMBOL(fpga_write); diff -Nru a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/gpio.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,755 @@ +/* + * linux/arch/arm/mach-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* + * OMAP1510 GPIO registers + */ +#define OMAP1510_GPIO_BASE 0xfffce000 +#define OMAP1510_GPIO_DATA_INPUT 0x00 +#define OMAP1510_GPIO_DATA_OUTPUT 0x04 +#define OMAP1510_GPIO_DIR_CONTROL 0x08 +#define OMAP1510_GPIO_INT_CONTROL 0x0c +#define OMAP1510_GPIO_INT_MASK 0x10 +#define OMAP1510_GPIO_INT_STATUS 0x14 +#define OMAP1510_GPIO_PIN_CONTROL 0x18 + +#define OMAP1510_IH_GPIO_BASE 64 + +/* + * OMAP1610 specific GPIO registers + */ +#define OMAP1610_GPIO1_BASE 0xfffbe400 +#define OMAP1610_GPIO2_BASE 0xfffbec00 +#define OMAP1610_GPIO3_BASE 0xfffbb400 +#define OMAP1610_GPIO4_BASE 0xfffbbc00 +#define OMAP1610_GPIO_REVISION 0x0000 +#define OMAP1610_GPIO_SYSCONFIG 0x0010 +#define OMAP1610_GPIO_SYSSTATUS 0x0014 +#define OMAP1610_GPIO_IRQSTATUS1 0x0018 +#define OMAP1610_GPIO_IRQENABLE1 0x001c +#define OMAP1610_GPIO_DATAIN 0x002c +#define OMAP1610_GPIO_DATAOUT 0x0030 +#define OMAP1610_GPIO_DIRECTION 0x0034 +#define OMAP1610_GPIO_EDGE_CTRL1 0x0038 +#define OMAP1610_GPIO_EDGE_CTRL2 0x003c +#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c +#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 +#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc +#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 + +/* + * OMAP730 specific GPIO registers + */ +#define OMAP730_GPIO1_BASE 0xfffbc000 +#define OMAP730_GPIO2_BASE 0xfffbc800 +#define OMAP730_GPIO3_BASE 0xfffbd000 +#define OMAP730_GPIO4_BASE 0xfffbd800 +#define OMAP730_GPIO5_BASE 0xfffbe000 +#define OMAP730_GPIO6_BASE 0xfffbe800 +#define OMAP730_GPIO_DATA_INPUT 0x00 +#define OMAP730_GPIO_DATA_OUTPUT 0x04 +#define OMAP730_GPIO_DIR_CONTROL 0x08 +#define OMAP730_GPIO_INT_CONTROL 0x0c +#define OMAP730_GPIO_INT_MASK 0x10 +#define OMAP730_GPIO_INT_STATUS 0x14 + +#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff) + +struct gpio_bank { + u32 base; + u16 irq; + u16 virtual_irq_start; + u8 method; + u32 reserved_map; + spinlock_t lock; +}; + +#define METHOD_MPUIO 0 +#define METHOD_GPIO_1510 1 +#define METHOD_GPIO_1610 2 +#define METHOD_GPIO_730 3 + +#ifdef CONFIG_ARCH_OMAP1610 +static struct gpio_bank gpio_bank_1610[5] = { + { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, + { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, + { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, + { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, + { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, +}; +#endif + +#ifdef CONFIG_ARCH_OMAP1510 +static struct gpio_bank gpio_bank_1510[2] = { + { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, + { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } +}; +#endif + +#ifdef CONFIG_ARCH_OMAP730 +static struct gpio_bank gpio_bank_730[7] = { + { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, + { OMAP730_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, + { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, + { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, + { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, + { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, + { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, +}; +#endif + +static struct gpio_bank *gpio_bank; +static int gpio_bank_count; + +static inline struct gpio_bank *get_gpio_bank(int gpio) +{ +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + if (OMAP_GPIO_IS_MPUIO(gpio)) + return &gpio_bank[0]; + return &gpio_bank[1]; + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + if (OMAP_GPIO_IS_MPUIO(gpio)) + return &gpio_bank[0]; + return &gpio_bank[1 + (gpio >> 4)]; + } +#endif +#ifdef CONFIG_ARCH_OMAP730 + if (cpu_is_omap730()) { + if (OMAP_GPIO_IS_MPUIO(gpio)) + return &gpio_bank[0]; + return &gpio_bank[1 + (gpio >> 5)]; + } +#endif +} + +static inline int get_gpio_index(int gpio) +{ + if (cpu_is_omap730()) + return gpio & 0x1f; + else + return gpio & 0x0f; +} + +static inline int gpio_valid(int gpio) +{ + if (gpio < 0) + return -1; + if (OMAP_GPIO_IS_MPUIO(gpio)) { + if ((gpio & OMAP_MPUIO_MASK) > 16) + return -1; + return 0; + } +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510() && gpio < 16) + return 0; +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610() && gpio < 64) + return 0; +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap730() && gpio < 192) + return 0; +#endif + return -1; +} + +static int check_gpio(int gpio) +{ + if (unlikely(gpio_valid(gpio)) < 0) { + printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); + dump_stack(); + return -1; + } + return 0; +} + +static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) +{ + u32 reg = bank->base; + u32 l; + + switch (bank->method) { + case METHOD_MPUIO: + reg += OMAP_MPUIO_IO_CNTL; + break; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_DIR_CONTROL; + break; + case METHOD_GPIO_1610: + reg += OMAP1610_GPIO_DIRECTION; + break; + case METHOD_GPIO_730: + reg += OMAP730_GPIO_DIR_CONTROL; + break; + } + l = __raw_readl(reg); + if (is_input) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); +} + +void omap_set_gpio_direction(int gpio, int is_input) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + _set_gpio_direction(bank, get_gpio_index(gpio), is_input); + spin_unlock(&bank->lock); +} + +static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) +{ + u32 reg = bank->base; + u32 l = 0; + + switch (bank->method) { + case METHOD_MPUIO: + reg += OMAP_MPUIO_OUTPUT_REG; + l = __raw_readl(reg); + if (enable) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + break; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_DATA_OUTPUT; + l = __raw_readl(reg); + if (enable) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + break; + case METHOD_GPIO_1610: + if (enable) + reg += OMAP1610_GPIO_SET_DATAOUT; + else + reg += OMAP1610_GPIO_CLEAR_DATAOUT; + l = 1 << gpio; + break; + case METHOD_GPIO_730: + reg += OMAP730_GPIO_DATA_OUTPUT; + l = __raw_readl(reg); + if (enable) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + break; + default: + BUG(); + return; + } + __raw_writel(l, reg); +} + +void omap_set_gpio_dataout(int gpio, int enable) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + _set_gpio_dataout(bank, get_gpio_index(gpio), enable); + spin_unlock(&bank->lock); +} + +int omap_get_gpio_datain(int gpio) +{ + struct gpio_bank *bank; + u32 reg; + + if (check_gpio(gpio) < 0) + return -1; + bank = get_gpio_bank(gpio); + reg = bank->base; + switch (bank->method) { + case METHOD_MPUIO: + reg += OMAP_MPUIO_INPUT_LATCH; + break; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_DATA_INPUT; + break; + case METHOD_GPIO_1610: + reg += OMAP1610_GPIO_DATAIN; + break; + default: + BUG(); + return -1; + } + return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; +} + +static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge) +{ + u32 reg = bank->base; + u32 l; + + switch (bank->method) { + case METHOD_MPUIO: + reg += OMAP_MPUIO_GPIO_INT_EDGE_REG; + l = __raw_readl(reg); + if (edge == OMAP_GPIO_RISING_EDGE) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); + break; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_INT_CONTROL; + l = __raw_readl(reg); + if (edge == OMAP_GPIO_RISING_EDGE) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); + break; + case METHOD_GPIO_1610: + edge &= 0x03; + if (gpio & 0x08) + reg += OMAP1610_GPIO_EDGE_CTRL2; + else + reg += OMAP1610_GPIO_EDGE_CTRL1; + gpio &= 0x07; + l = __raw_readl(reg); + l &= ~(3 << (gpio << 1)); + l |= edge << (gpio << 1); + __raw_writel(l, reg); + break; + case METHOD_GPIO_730: + reg += OMAP730_GPIO_INT_CONTROL; + l = __raw_readl(reg); + if (edge == OMAP_GPIO_RISING_EDGE) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); + break; + default: + BUG(); + return; + } +} + +void omap_set_gpio_edge_ctrl(int gpio, int edge) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge); + spin_unlock(&bank->lock); +} + + +static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio) +{ + u32 reg = bank->base, l; + + switch (bank->method) { + case METHOD_MPUIO: + l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG); + return (l & (1 << gpio)) ? + OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; + case METHOD_GPIO_1510: + l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL); + return (l & (1 << gpio)) ? + OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; + case METHOD_GPIO_1610: + if (gpio & 0x08) + reg += OMAP1610_GPIO_EDGE_CTRL2; + else + reg += OMAP1610_GPIO_EDGE_CTRL1; + return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03; + case METHOD_GPIO_730: + l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL); + return (l & (1 << gpio)) ? + OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; + default: + BUG(); + return -1; + } +} + +static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) +{ + u32 reg = bank->base; + + switch (bank->method) { + case METHOD_MPUIO: + /* MPUIO irqstatus cannot be cleared one bit at a time, + * so do nothing here */ + return; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_INT_STATUS; + break; + case METHOD_GPIO_1610: + reg += OMAP1610_GPIO_IRQSTATUS1; + break; + case METHOD_GPIO_730: + reg += OMAP730_GPIO_INT_STATUS; + break; + default: + BUG(); + return; + } + __raw_writel(1 << get_gpio_index(gpio), reg); +} + +static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) +{ + u32 reg = bank->base; + u32 l; + + switch (bank->method) { + case METHOD_MPUIO: + reg += OMAP_MPUIO_GPIO_MASKIT; + l = __raw_readl(reg); + if (enable) + l &= ~(1 << gpio); + else + l |= 1 << gpio; + break; + case METHOD_GPIO_1510: + reg += OMAP1510_GPIO_INT_MASK; + l = __raw_readl(reg); + if (enable) + l &= ~(1 << gpio); + else + l |= 1 << gpio; + break; + case METHOD_GPIO_1610: + if (enable) { + reg += OMAP1610_GPIO_SET_IRQENABLE1; + _clear_gpio_irqstatus(bank, gpio); + } else + reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; + l = 1 << gpio; + break; + case METHOD_GPIO_730: + reg += OMAP730_GPIO_INT_MASK; + l = __raw_readl(reg); + if (enable) + l &= ~(1 << gpio); + else + l |= 1 << gpio; + break; + default: + BUG(); + return; + } + __raw_writel(l, reg); +} + +int omap_request_gpio(int gpio) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return -EINVAL; + + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { + printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); + dump_stack(); + spin_unlock(&bank->lock); + return -1; + } + bank->reserved_map |= (1 << get_gpio_index(gpio)); +#ifdef CONFIG_ARCH_OMAP1510 + if (bank->method == METHOD_GPIO_1510) { + u32 reg; + + /* Claim the pin for the ARM */ + reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; + __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); + } +#endif + spin_unlock(&bank->lock); + + return 0; +} + +void omap_free_gpio(int gpio) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { + printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); + dump_stack(); + spin_unlock(&bank->lock); + return; + } + bank->reserved_map &= ~(1 << get_gpio_index(gpio)); + _set_gpio_direction(bank, get_gpio_index(gpio), 1); + _set_gpio_irqenable(bank, get_gpio_index(gpio), 0); + spin_unlock(&bank->lock); +} + +static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + u32 isr_reg = 0; + struct gpio_bank *bank = (struct gpio_bank *) desc->data; + + /* + * Acknowledge the parent IRQ. + */ + desc->chip->ack(irq); + + /* Since the level 1 GPIO interrupt cascade (IRQ14) is configured as + * edge-sensitive, we need to unmask it here in order to avoid missing + * any additional GPIO interrupts that might occur after the last time + * we check for pending GPIO interrupts here. + * We are relying on the fact that this interrupt handler was installed + * with the SA_INTERRUPT flag so that interrupts are disabled at the + * CPU while it is executing. + */ + desc->chip->unmask(irq); + + if (bank->method == METHOD_MPUIO) + isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; +#ifdef CONFIG_ARCH_OMAP1510 + if (bank->method == METHOD_GPIO_1510) + isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (bank->method == METHOD_GPIO_1610) + isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; +#endif +#ifdef CONFIG_ARCH_OMAP730 + if (bank->method == METHOD_GPIO_730) + isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; +#endif + for (;;) { + u32 isr = __raw_readl(isr_reg); + unsigned int gpio_irq; + + if (!isr) + break; + gpio_irq = bank->virtual_irq_start; + + for (; isr != 0; isr >>= 1, gpio_irq++) { + if (isr & 1) { + struct irqdesc *d = irq_desc + gpio_irq; + d->handle(gpio_irq, d, regs); + } + } + } +} + +static void gpio_ack_irq(unsigned int irq) +{ + unsigned int gpio = irq - IH_GPIO_BASE; + struct gpio_bank *bank = get_gpio_bank(gpio); + +#ifdef CONFIG_ARCH_OMAP1510 + if (bank->method == METHOD_GPIO_1510) + __raw_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS); +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (bank->method == METHOD_GPIO_1610) + __raw_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1); +#endif +#ifdef CONFIG_ARCH_OMAP730 + if (bank->method == METHOD_GPIO_730) + __raw_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS); +#endif +} + +static void gpio_mask_irq(unsigned int irq) +{ + unsigned int gpio = irq - IH_GPIO_BASE; + struct gpio_bank *bank = get_gpio_bank(gpio); + + _set_gpio_irqenable(bank, get_gpio_index(gpio), 0); +} + +static void gpio_unmask_irq(unsigned int irq) +{ + unsigned int gpio = irq - IH_GPIO_BASE; + struct gpio_bank *bank = get_gpio_bank(gpio); + + if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) { + printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n", + gpio); + _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE); + } + _set_gpio_irqenable(bank, get_gpio_index(gpio), 1); +} + +static void mpuio_ack_irq(unsigned int irq) +{ + /* The ISR is reset automatically, so do nothing here. */ +} + +static void mpuio_mask_irq(unsigned int irq) +{ + unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); + struct gpio_bank *bank = get_gpio_bank(gpio); + + _set_gpio_irqenable(bank, gpio, 0); +} + +static void mpuio_unmask_irq(unsigned int irq) +{ + unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); + struct gpio_bank *bank = get_gpio_bank(gpio); + + _set_gpio_irqenable(bank, gpio, 1); +} + +static struct irqchip gpio_irq_chip = { + .ack = gpio_ack_irq, + .mask = gpio_mask_irq, + .unmask = gpio_unmask_irq, +}; + +static struct irqchip mpuio_irq_chip = { + .ack = mpuio_ack_irq, + .mask = mpuio_mask_irq, + .unmask = mpuio_unmask_irq +}; + +static int initialized = 0; + +static int __init _omap_gpio_init(void) +{ + int i; + struct gpio_bank *bank; + + initialized = 1; + +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + printk(KERN_INFO "OMAP1510 GPIO hardware\n"); + gpio_bank_count = 2; + gpio_bank = gpio_bank_1510; + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + int rev; + + gpio_bank_count = 5; + gpio_bank = gpio_bank_1610; + rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); + printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", + (rev >> 4) & 0x0f, rev & 0x0f); + } +#endif +#ifdef CONFIG_ARCH_OMAP730 + if (cpu_is_omap730()) { + printk(KERN_INFO "OMAP730 GPIO hardware\n"); + gpio_bank_count = 7; + gpio_bank = gpio_bank_730; + } +#endif + for (i = 0; i < gpio_bank_count; i++) { + int j, gpio_count = 16; + + bank = &gpio_bank[i]; + bank->reserved_map = 0; + spin_lock_init(&bank->lock); + if (bank->method == METHOD_MPUIO) { + __raw_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); + } +#ifdef CONFIG_ARCH_OMAP1510 + if (bank->method == METHOD_GPIO_1510) { + __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); + __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (bank->method == METHOD_GPIO_1610) { + __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); + __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); + } +#endif +#ifdef CONFIG_ARCH_OMAP730 + if (bank->method == METHOD_GPIO_730) { + __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); + __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); + + gpio_count = 32; /* 730 has 32-bit GPIOs */ + } +#endif + for (j = bank->virtual_irq_start; + j < bank->virtual_irq_start + gpio_count; j++) { + if (bank->method == METHOD_MPUIO) + set_irq_chip(j, &mpuio_irq_chip); + else + set_irq_chip(j, &gpio_irq_chip); + set_irq_handler(j, do_level_IRQ); + set_irq_flags(j, IRQF_VALID); + } + set_irq_chained_handler(bank->irq, gpio_irq_handler); + set_irq_data(bank->irq, bank); + } + + /* Enable system clock for GPIO module. + * The CAM_CLK_CTRL_REG *is* really the right place. */ + if (cpu_is_omap1610()) + __raw_writel(__raw_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG); + + return 0; +} + +/* + * This may get called early from board specific init + */ +int omap_gpio_init(void) +{ + if (!initialized) + return _omap_gpio_init(); + else + return 0; +} + +EXPORT_SYMBOL(omap_gpio_init); +EXPORT_SYMBOL(omap_request_gpio); +EXPORT_SYMBOL(omap_free_gpio); + +arch_initcall(omap_gpio_init); diff -Nru a/arch/arm/mach-omap/innovator1510.c b/arch/arm/mach-omap/innovator1510.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/innovator1510.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,99 @@ +/* + * linux/arch/arm/mach-omap/innovator1510.c + * + * Board specific inits for OMAP-1510 Innovator + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "common.h" + +extern int omap_gpio_init(void); + +void innovator_init_irq(void) +{ + omap_init_irq(); + omap_gpio_init(); + fpga_init_irq(); +} + +static struct resource smc91x_resources[] = { + [0] = { + .start = OMAP1510P1_FPGA_ETHR_START, /* Physical */ + .end = OMAP1510P1_FPGA_ETHR_START + 16, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_ETHER, + .end = INT_ETHER, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, +}; + +static void __init innovator_init(void) +{ + if (!machine_is_innovator()) + return; + + (void) platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +/* Only FPGA needs to be mapped here. All others are done with ioremap */ +static struct map_desc innovator_io_desc[] __initdata = { +{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE, + MT_DEVICE }, +}; + +static void __init innovator_map_io(void) +{ + omap_map_io(); + iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc)); + + /* Dump the Innovator FPGA rev early - useful info for support. */ + printk("Innovator FPGA Rev %d.%d Board Rev %d\n", + fpga_read(OMAP1510P1_FPGA_REV_HIGH), + fpga_read(OMAP1510P1_FPGA_REV_LOW), + fpga_read(OMAP1510P1_FPGA_BOARD_REV)); +} + +MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1510") + MAINTAINER("MontaVista Software, Inc.") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(innovator_map_io) + INITIRQ(innovator_init_irq) + INIT_MACHINE(innovator_init) +MACHINE_END diff -Nru a/arch/arm/mach-omap/innovator1610.c b/arch/arm/mach-omap/innovator1610.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/innovator1610.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,91 @@ +/* + * linux/arch/arm/mach-omap/innovator1610.c + * + * This file contains Innovator-specific code. + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "common.h" + +void +innovator_init_irq(void) +{ + omap_init_irq(); +} + +static struct resource smc91x_resources[] = { + [0] = { + .start = OMAP1610_ETHR_START, /* Physical */ + .end = OMAP1610_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, /* Really GPIO 0 */ + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, +}; + +static void __init innovator_init(void) +{ + if (!machine_is_innovator()) + return; + + (void) platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static struct map_desc innovator_io_desc[] __initdata = { +{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE }, +{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE, + MT_DEVICE }, +}; + +static void __init innovator_map_io(void) +{ + omap_map_io(); + iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc)); +} + +MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1610") + MAINTAINER("MontaVista Software, Inc.") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(innovator_map_io) + INITIRQ(innovator_init_irq) + INIT_MACHINE(innovator_init) +MACHINE_END + diff -Nru a/arch/arm/mach-omap/irq.c b/arch/arm/mach-omap/irq.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/irq.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,224 @@ +/* + * linux/arch/arm/mach-omap/irq.c + * + * Interrupt handler for OMAP-1510 and 1610 + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon + * + * Modified for OMAP-1610 by Tony Lindgren + * GPIO interrupt handler moved to gpio.c for OMAP-1610 by Juha Yrjola + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define NUM_IRQS IH_BOARD_BASE + +static void mask_irq(unsigned int irq); +static void unmask_irq(unsigned int irq); +static void ack_irq(unsigned int irq); + +static inline void +write_ih(int level, int reg, u32 value) +{ + if (cpu_is_omap1510()) { + __raw_writel(value, + (IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) + + (reg)))); + } else { + if (level) { + __raw_writel(value, + IO_ADDRESS(OMAP_IH2_BASE + ((level - 1) << 8) + + reg)); + } else { + __raw_writel(value, IO_ADDRESS(OMAP_IH1_BASE + reg)); + } + } +} + +static inline u32 +read_ih(int level, int reg) +{ + if (cpu_is_omap1510()) { + return __raw_readl((IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) + + (reg)))); + } else { + if (level) { + return __raw_readl(IO_ADDRESS(OMAP_IH2_BASE + + ((level - 1) << 8) + reg)); + } else { + return __raw_readl(IO_ADDRESS(OMAP_IH1_BASE + reg)); + } + } +} + +static inline int +get_level(int irq) +{ + if (cpu_is_omap1510()) { + return (((irq) < IH2_BASE) ? 0 : 1); + } else { + if (irq < IH2_BASE) + return 0; + else { + return (irq >> 5); + } + } +} + +static inline int +get_irq_num(int irq) +{ + if (cpu_is_omap1510()) { + return (((irq) < IH2_BASE) ? irq : irq - IH2_BASE); + } else { + return irq & 0x1f; + } +} + +static void +mask_irq(unsigned int irq) +{ + int level = get_level(irq); + int irq_num = get_irq_num(irq); + u32 mask = read_ih(level, IRQ_MIR) | (1 << irq_num); + write_ih(level, IRQ_MIR, mask); +} + +static void +ack_irq(unsigned int irq) +{ + int level = get_level(irq); + + if (level > 1) + level = 1; + do { + write_ih(level, IRQ_CONTROL_REG, 0x1); + /* + * REVISIT: So says the TRM: + * if (level) write_ih(0, ITR, 0); + */ + } while (level--); +} + +void +unmask_irq(unsigned int irq) +{ + int level = get_level(irq); + int irq_num = get_irq_num(irq); + u32 mask = read_ih(level, IRQ_MIR) & ~(1 << irq_num); + + write_ih(level, IRQ_MIR, mask); +} + +static void +mask_ack_irq(unsigned int irq) +{ + mask_irq(irq); + ack_irq(irq); +} + +static struct irqchip omap_normal_irq = { + .ack = mask_ack_irq, + .mask = mask_irq, + .unmask = unmask_irq, +}; + +static void +irq_priority(int irq, int fiq, int priority, int trigger) +{ + int level, irq_num; + unsigned long reg_value, reg_addr; + + level = get_level(irq); + irq_num = get_irq_num(irq); + /* FIQ is only available on level 0 interrupts */ + fiq = level ? 0 : (fiq & 0x1); + reg_value = (fiq) | ((priority & 0x1f) << 2) | + ((trigger & 0x1) << 1); + reg_addr = (IRQ_ILR0 + irq_num * 0x4); + write_ih(level, reg_addr, reg_value); +} + +void __init +omap_init_irq(void) +{ + int i, irq_count, irq_bank_count = 0; + uint *trigger; + + if (cpu_is_omap1510()) { + static uint trigger_1510[2] = { + 0xb3febfff, 0xffbfffed + }; + irq_bank_count = 2; + irq_count = 64; + trigger = trigger_1510; + } + if (cpu_is_omap1610()) { + static uint trigger_1610[5] = { + 0xb3fefe8f, 0xfffff7ff, 0xffffffff + }; + irq_bank_count = 5; + irq_count = 160; + trigger = trigger_1610; + } + if (cpu_is_omap730()) { + static uint trigger_730[] = { + 0xb3f8e22f, 0xfdb9c1f2, 0x800040f3 + }; + irq_bank_count = 3; + irq_count = 96; + trigger = trigger_730; + } + + for (i = 0; i < irq_bank_count; i++) { + /* Mask and clear all interrupts */ + write_ih(i, IRQ_MIR, ~0x0); + write_ih(i, IRQ_ITR, 0x0); + } + + /* Clear any pending interrupts */ + write_ih(1, IRQ_CONTROL_REG, 3); + write_ih(0, IRQ_CONTROL_REG, 3); + + for (i = 0; i < irq_count; i++) { + set_irq_chip(i, &omap_normal_irq); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID); + + irq_priority(i, 0, 0, trigger[get_level(i)] >> get_irq_num(i) & 1); + } + unmask_irq(INT_IH2_IRQ); +} diff -Nru a/arch/arm/mach-omap/leds-innovator.c b/arch/arm/mach-omap/leds-innovator.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/leds-innovator.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,103 @@ +/* + * linux/arch/arm/mach-omap/leds-innovator.c + */ +#include +#include + +#include +#include +#include + +#include "leds.h" + + +#define LED_STATE_ENABLED 1 +#define LED_STATE_CLAIMED 2 + +static unsigned int led_state; +static unsigned int hw_led_state; + +void innovator_leds_event(led_event_t evt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch (evt) { + case led_start: + hw_led_state = 0; + led_state = LED_STATE_ENABLED; + break; + + case led_stop: + led_state &= ~LED_STATE_ENABLED; + hw_led_state = 0; + break; + + case led_claim: + led_state |= LED_STATE_CLAIMED; + hw_led_state = 0; + break; + + case led_release: + led_state &= ~LED_STATE_CLAIMED; + hw_led_state = 0; + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state ^= 0; + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state |= 0; + break; + + case led_idle_end: + if (!(led_state & LED_STATE_CLAIMED)) + hw_led_state &= ~0; + break; +#endif + + case led_halted: + break; + + case led_green_on: + if (led_state & LED_STATE_CLAIMED) + hw_led_state &= ~0; + break; + + case led_green_off: + if (led_state & LED_STATE_CLAIMED) + hw_led_state |= 0; + break; + + case led_amber_on: + break; + + case led_amber_off: + break; + + case led_red_on: + if (led_state & LED_STATE_CLAIMED) + hw_led_state &= ~0; + break; + + case led_red_off: + if (led_state & LED_STATE_CLAIMED) + hw_led_state |= 0; + break; + + default: + break; + } + + if (led_state & LED_STATE_ENABLED) + ; + + local_irq_restore(flags); +} diff -Nru a/arch/arm/mach-omap/leds-perseus2.c b/arch/arm/mach-omap/leds-perseus2.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/leds-perseus2.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,103 @@ +/* + * linux/arch/arm/mach-omap/leds-perseus2.c + * + * Copyright 2003 by Texas Instruments Incorporated + * + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "leds.h" + +void perseus2_leds_event(led_event_t evt) +{ + unsigned long flags; + static unsigned long hw_led_state = 0; + + local_irq_save(flags); + + switch (evt) { + case led_start: + hw_led_state |= OMAP730_FPGA_LED_STARTSTOP; + break; + + case led_stop: + hw_led_state &= ~OMAP730_FPGA_LED_STARTSTOP; + break; + + case led_claim: + hw_led_state |= OMAP730_FPGA_LED_CLAIMRELEASE; + break; + + case led_release: + hw_led_state &= ~OMAP730_FPGA_LED_CLAIMRELEASE; + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: + /* + * Toggle Timer LED + */ + if (hw_led_state & OMAP730_FPGA_LED_TIMER) + hw_led_state &= ~OMAP730_FPGA_LED_TIMER; + else + hw_led_state |= OMAP730_FPGA_LED_TIMER; + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: + hw_led_state |= OMAP730_FPGA_LED_IDLE; + break; + + case led_idle_end: + hw_led_state &= ~OMAP730_FPGA_LED_IDLE; + break; +#endif + + case led_halted: + if (hw_led_state & OMAP730_FPGA_LED_HALTED) + hw_led_state &= ~OMAP730_FPGA_LED_HALTED; + else + hw_led_state |= OMAP730_FPGA_LED_HALTED; + break; + + case led_green_on: + break; + + case led_green_off: + break; + + case led_amber_on: + break; + + case led_amber_off: + break; + + case led_red_on: + break; + + case led_red_off: + break; + + default: + break; + } + + + /* + * Actually burn the LEDs + */ + __raw_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS); + + local_irq_restore(flags); +} diff -Nru a/arch/arm/mach-omap/leds.c b/arch/arm/mach-omap/leds.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/leds.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-omap/leds.c + * + * OMAP LEDs dispatcher + */ +#include + +#include +#include + +#include "leds.h" + +static int __init +omap1510_leds_init(void) +{ + if (machine_is_innovator()) + leds_event = innovator_leds_event; + + leds_event(led_start); + return 0; +} + +__initcall(omap1510_leds_init); diff -Nru a/arch/arm/mach-omap/leds.h b/arch/arm/mach-omap/leds.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/leds.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,2 @@ +extern void innovator_leds_event(led_event_t evt); +extern void perseus2_leds_event(led_event_t evt); diff -Nru a/arch/arm/mach-omap/mux.c b/arch/arm/mach-omap/mux.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/mux.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,124 @@ +/* + * linux/arch/arm/mach-omap/mux.c + * + * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h + * + * Copyright (C) 2003 Nokia Corporation + * + * Written by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include + +#define __MUX_C__ +#include + +static spinlock_t mux_spin_lock = SPIN_LOCK_UNLOCKED; + +/* + * Sets the Omap MUX and PULL_DWN registers based on the table + */ +int omap_cfg_reg(const reg_cfg_t reg_cfg) +{ +#ifdef CONFIG_OMAP_MUX + unsigned long flags; + reg_cfg_set *cfg; + unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, + pull_orig = 0, pull = 0; + + cfg = ®_cfg_table[reg_cfg]; + + /* + * We do a pretty long section here with lock on, but pin muxing + * should only happen on driver init for each driver, so it's not time + * critical. + */ + spin_lock_irqsave(&mux_spin_lock, flags); + + /* Check the mux register in question */ + if (cfg->mux_reg) { + reg_orig = __raw_readl(cfg->mux_reg); + + /* The mux registers always seem to be 3 bits long */ + reg = reg_orig & ~(0x7 << cfg->mask_offset); + + reg |= (cfg->mask << cfg->mask_offset); + + __raw_writel(reg, cfg->mux_reg); + } + + /* Check for pull up or pull down selection on 1610 */ + if (!cpu_is_omap1510()) { + if (cfg->pu_pd_reg && cfg->pull_val) { + pu_pd_orig = __raw_readl(cfg->pu_pd_reg); + if (cfg->pu_pd_val) { + /* Use pull up */ + pu_pd = pu_pd_orig | (1 << cfg->pull_bit); + } else { + /* Use pull down */ + pu_pd = pu_pd_orig & ~(1 << cfg->pull_bit); + } + __raw_writel(pu_pd, cfg->pu_pd_reg); + } + } + + /* Check for an associated pull down register */ + if (cfg->pull_reg) { + pull_orig = __raw_readl(cfg->pull_reg); + + if (cfg->pull_val) { + /* Low bit = pull enabled */ + pull = pull_orig & ~(1 << cfg->pull_bit); + } else { + /* High bit = pull disabled */ + pull = pull_orig | (1 << cfg->pull_bit); + } + + __raw_writel(pull, cfg->pull_reg); + } + +#ifdef CONFIG_OMAP_MUX_DEBUG + if (cfg->debug) { + printk("Omap: Setting register %s\n", cfg->name); + printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); + + if (!cpu_is_omap1510()) { + if (cfg->pu_pd_reg && cfg->pull_val) { + printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->pu_pd_name, cfg->pu_pd_reg, + pu_pd_orig, pu_pd); + } + } + + printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->pull_name, cfg->pull_reg, pull_orig, pull); + } +#endif + + spin_unlock_irqrestore(&mux_spin_lock, flags); + +#endif + return 0; +} + +EXPORT_SYMBOL(omap_cfg_reg); diff -Nru a/arch/arm/mach-omap/ocpi.c b/arch/arm/mach-omap/ocpi.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/ocpi.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,116 @@ +/* + * linux/arch/arm/mach-omap/ocpi.c + * + * Minimal OCP bus support for OMAP-1610 + * + * Copyright (C) 2003 - 2004 Nokia Corporation + * Written by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define OCPI_BASE 0xfffec320 +#define OCPI_FAULT (OCPI_BASE + 0x00) +#define OCPI_CMD_FAULT (OCPI_BASE + 0x04) +#define OCPI_SINT0 (OCPI_BASE + 0x08) +#define OCPI_TABORT (OCPI_BASE + 0x0c) +#define OCPI_SINT1 (OCPI_BASE + 0x10) +#define OCPI_PROT (OCPI_BASE + 0x14) +#define OCPI_SEC (OCPI_BASE + 0x18) + +#define EN_OCPI_CK (1 << 0) +#define IDLOCPI_ARM (1 << 1) + +/* USB OHCI OCPI access error registers */ +#define HOSTUEADDR 0xfffba0e0 +#define HOSTUESTATUS 0xfffba0e4 + +/* + * Enables device access to OMAP buses via the OCPI bridge + * FIXME: Add locking + */ +int ocpi_enable(void) +{ + unsigned int val; + + /* Make sure there's clock for OCPI */ + val = __raw_readl(ARM_IDLECT3); + val |= EN_OCPI_CK; + val &= ~IDLOCPI_ARM; + __raw_writel(val, ARM_IDLECT3); + + /* Enable access for OHCI in OCPI */ + val = __raw_readl(OCPI_PROT); + val &= ~0xff; + //val &= (1 << 0); /* Allow access only to EMIFS */ + __raw_writel(val, OCPI_PROT); + + val = __raw_readl(OCPI_SEC); + val &= ~0xff; + __raw_writel(val, OCPI_SEC); + + val = __raw_readl(OCPI_SEC); + val |= 0; + __raw_writel(val, OCPI_SEC); + + val = __raw_readl(OCPI_SINT0); + val |= 0; + __raw_writel(val, OCPI_SINT1); + + return 0; +} +EXPORT_SYMBOL(ocpi_enable); + +int ocpi_status(void) +{ + printk("OCPI: addr: 0x%08x cmd: 0x%08x\n" + " ohci-addr: 0x%08x ohci-status: 0x%08x\n", + __raw_readl(OCPI_FAULT), __raw_readl(OCPI_CMD_FAULT), + __raw_readl(HOSTUEADDR), __raw_readl(HOSTUESTATUS)); + + return 1; +} +EXPORT_SYMBOL(ocpi_status); + +static int __init omap_ocpi_init(void) +{ + ocpi_enable(); + printk("OMAP OCPI interconnect driver loaded\n"); + + return 0; +} + +static void __exit omap_ocpi_exit(void) +{ + /* FIXME: Disable OCPI */ +} + +MODULE_AUTHOR("Tony Lindgren "); +MODULE_DESCRIPTION("OMAP OCPI bus controller module"); +MODULE_LICENSE("GPL"); +module_init(omap_ocpi_init); +module_exit(omap_ocpi_exit); diff -Nru a/arch/arm/mach-omap/omap-generic.c b/arch/arm/mach-omap/omap-generic.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/omap-generic.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,77 @@ +/* + * linux/arch/arm/mach-omap/generic.c + * + * Modified from innovator.c + * + * Code for generic OMAP board. Should work on many OMAP systems where + * the device drivers take care of all the necessary hardware initialization. + * Do not put any board specific code to this file; create a new machine + * type if you need custom low-level initializations. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "common.h" + +static void __init omap_generic_init_irq(void) +{ + omap_init_irq(); +} + +/* + * Muxes the serial ports on + */ +static void __init omap_early_serial_init(void) +{ + omap_cfg_reg(UART1_TX); + omap_cfg_reg(UART1_RTS); + + omap_cfg_reg(UART2_TX); + omap_cfg_reg(UART2_RTS); + + omap_cfg_reg(UART3_TX); + omap_cfg_reg(UART3_RX); +} + +static void __init omap_generic_init(void) +{ + if (!machine_is_omap_generic()) + return; + + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on + * if not needed. + */ + if (cpu_is_omap1510()) { + omap_early_serial_init(); + } +} + +static void __init omap_generic_map_io(void) +{ + omap_map_io(); +} + +MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610") + MAINTAINER("Tony Lindgren ") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(omap_generic_map_io) + INITIRQ(omap_generic_init_irq) + INIT_MACHINE(omap_generic_init) +MACHINE_END diff -Nru a/arch/arm/mach-omap/omap-perseus2.c b/arch/arm/mach-omap/omap-perseus2.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/arm/mach-omap/omap-perseus2.c Sun Apr 4 18:51:05 2004 @@ -0,0 +1,116 @@ +/* + * linux/arch/arm/mach-omap/omap-perseus2.c + * + * Modified from omap-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "common.h" + +void omap_perseus2_init_irq(void) +{ + omap_init_irq(); +} + +static struct resource smc91x_resources[] = { + [0] = { + .start = OMAP730_FPGA_ETHR_START, /* Physical */ + .end = OMAP730_FPGA_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, + .end = 0, + .flags = INT_ETHER, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, +}; + +static void __init omap_perseus2_init(void) +{ + if (!machine_is_omap_perseus2()) + return; + + (void) platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +/* Only FPGA needs to be mapped here. All others are done with ioremap */ +static struct map_desc omap_perseus2_io_desc[] __initdata = { + {OMAP730_FPGA_BASE, OMAP730_FPGA_START, OMAP730_FPGA_SIZE, + MT_DEVICE}, +}; + +static void __init omap_perseus2_map_io(void) +{ + omap_map_io(); + iotable_init(omap_perseus2_io_desc, + ARRAY_SIZE(omap_perseus2_io_desc)); + + /* Early, board-dependent init */ + + /* + * Hold GSM Reset until needed + */ + *DSP_M_CTL &= ~1; + + /* + * UARTs -> done automagically by 8250 driver + */ + + /* + * CSx timings, GPIO Mux ... setup + */ + + /* Flash: CS0 timings setup */ + *((volatile __u32 *) OMAP_FLASH_CFG_0) = 0x0000fff3; + *((volatile __u32 *) OMAP_FLASH_ACFG_0) = 0x00000088; + + /* + * Ethernet support trough the debug board + * CS1 timings setup + */ + *((volatile __u32 *) OMAP_FLASH_CFG_1) = 0x0000fff3; + *((volatile __u32 *) OMAP_FLASH_ACFG_1) = 0x00000000; + + /* + * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, + * It is used as the Ethernet controller interrupt + */ + *((volatile __u32 *) PERSEUS2_IO_CONF_9) &= 0x1FFFFFFF; +} + +MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") + MAINTAINER("Kevin Hilman ") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(omap_perseus2_map_io) + INITIRQ(omap_perseus2_init_irq) + INIT_MACHINE(omap_perseus2_init) +MACHINE_END diff -Nru a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S --- a/arch/arm/mm/tlb-v4wbi.S Sun Apr 4 18:51:05 2004 +++ b/arch/arm/mm/tlb-v4wbi.S Sun Apr 4 18:51:05 2004 @@ -10,7 +10,7 @@ * ARM architecture version 4 and version 5 TLB handling functions. * These assume a split I/D TLBs, with a write buffer. * - * Processors: ARM920 ARM922 ARM926 XScale + * Processors: ARM920 ARM922 ARM925 ARM926 XScale */ #include #include diff -Nru a/include/asm-arm/arch-omap/bus.h b/include/asm-arm/arch-omap/bus.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/bus.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,97 @@ +/* + * linux/include/asm-arm/arch-omap/bus.h + * + * Virtual bus for OMAP. Allows better power management, such as managing + * shared clocks, and mapping of bus addresses to Local Bus addresses. + * + * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for + * examples on how to register drivers to this bus. + * + * Copyright (C) 2003 - 2004 Nokia Corporation + * Written by Tony Lindgren + * Portions of code based on sa1111.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_OMAP_BUS_H +#define __ASM_ARM_ARCH_OMAP_BUS_H + +extern struct bus_type omap_bus_types[]; + +/* + * Description for physical device + */ +struct omap_dev { + struct device dev; /* Standard device description */ + char *name; + unsigned int devid; /* OMAP device id */ + unsigned int busid; /* OMAP virtual busid */ + struct resource res; /* Standard resource description */ + void *mapbase; /* OMAP physical address */ + unsigned int irq[6]; /* OMAP interrupts */ + u64 *dma_mask; /* Used by USB OHCI only */ +}; + +#define OMAP_DEV(_d) container_of((_d), struct omap_dev, dev) + +#define omap_get_drvdata(d) dev_get_drvdata(&(d)->dev) +#define omap_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) + +/* + * Description for device driver + */ +struct omap_driver { + struct device_driver drv; /* Standard driver description */ + unsigned int devid; /* OMAP device id for bus */ + unsigned int busid; /* OMAP virtual busid */ + unsigned int clocks; /* OMAP shared clocks */ + int (*probe)(struct omap_dev *); + int (*remove)(struct omap_dev *); + int (*suspend)(struct omap_dev *, u32); + int (*resume)(struct omap_dev *); +}; + +#define OMAP_DRV(_d) container_of((_d), struct omap_driver, drv) +#define OMAP_DRIVER_NAME(_omapdev) ((_omapdev)->dev.driver->name) + +/* + * Device ID numbers for bus types + */ +#define OMAP_OCP_DEVID_USB 0 +#define OMAP_TIPB_DEVID_LCD 1 +#define OMAP_TIPB_DEVID_MMC 2 + +/* + * Virtual bus definitions for OMAP + */ +#define OMAP_NR_BUSES 2 + +#define OMAP_BUS_NAME_TIPB "tipb" +#define OMAP_BUS_NAME_LBUS "lbus" + +enum { + OMAP_BUS_TIPB = 0, + OMAP_BUS_LBUS, +}; + +/* See arch/arm/mach-omap/bus.c for the rest of the bus definitions. */ + +extern int omap_driver_register(struct omap_driver *driver); +extern void omap_driver_unregister(struct omap_driver *driver); +extern int omap_device_register(struct omap_dev *odev); +extern void omap_device_unregister(struct omap_dev *odev); + +#endif diff -Nru a/include/asm-arm/arch-omap/clocks.h b/include/asm-arm/arch-omap/clocks.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/clocks.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,216 @@ +/* + * OMAP clock interface + * + * Copyright (C) 2001 RidgeRun, Inc + * Written by Gordon McNutt + * Updated 2004 for Linux 2.6 by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARM_CLOCKS_H +#define __ASM_ARM_CLOCKS_H + +#include + +/* ARM_CKCTL bit shifts */ +#define PERDIV 0 +#define LCDDIV 2 +#define ARMDIV 4 +#define DSPDIV 6 +#define TCDIV 8 +#define DSPMMUDIV 10 +#define ARM_TIMXO 12 +#define EN_DSPCK 13 +#define ARM_INTHCK_SEL 14 /* REVISIT: Where is this used? */ + +/* ARM_IDLECT1 bit shifts */ +#define IDLWDT_ARM 0 +#define IDLXORP_ARM 1 +#define IDLPER_ARM 2 +#define IDLLCD_ARM 3 +#define IDLLB_ARM 4 +#define IDLHSAB_ARM 5 +#define IDLIF_ARM 6 +#define IDLDPLL_ARM 7 +#define IDLAPI_ARM 8 +#define IDLTIM_ARM 9 +#define SETARM_IDLE 11 + +/* ARM_IDLECT2 bit shifts */ +#define EN_WDTCK 0 +#define EN_XORPCK 1 +#define EN_PERCK 2 +#define EN_LCDCK 3 +#define EN_LBCK 4 +#define EN_HSABCK 5 +#define EN_APICK 6 +#define EN_TIMCK 7 +#define DMACK_REQ 8 +#define EN_GPIOCK 9 +#define EN_LBFREECK 10 + +/* + * OMAP clocks + */ +typedef enum { + /* Fixed system clock */ + OMAP_CLKIN = 0, + + /* DPLL1 */ + OMAP_CK_GEN1, OMAP_CK_GEN2, OMAP_CK_GEN3, + + /* TC usually needs to be checked before anything else */ + OMAP_TC_CK, + + /* CLKM1 */ + OMAP_ARM_CK, OMAP_MPUPER_CK, OMAP_ARM_GPIO_CK, OMAP_MPUXOR_CK, + OMAP_MPUTIM_CK, OMAP_MPUWD_CK, + + /* CLKM2 */ + OMAP_DSP_CK, OMAP_DSPMMU_CK, +#if 0 + /* Accessible only from the dsp */ + OMAP_DSPPER_CK, OMAP_GPIO_CK, OMAP_DSPXOR_CK, OMAP_DSPTIM_CK, + OMAP_DSPWD_CK, OMAP_UART_CK, +#endif + /* CLKM3 */ + OMAP_DMA_CK, OMAP_API_CK, OMAP_HSAB_CK, OMAP_LBFREE_CK, + OMAP_LB_CK, OMAP_LCD_CK +} ck_t; + +typedef enum { + /* Reset the MPU */ + OMAP_ARM_RST, + + /* Reset the DSP */ + OMAP_DSP_RST, + + /* Reset priority registers, EMIF config, and MPUI control logic */ + OMAP_API_RST, + + /* Reset DSP, MPU, and Peripherals */ + OMAP_SW_RST, +} reset_t; + +#define OMAP_CK_MIN OMAP_CLKIN +#define OMAP_CK_MAX OMAP_LCD_CK + +#if defined(CONFIG_OMAP_ARM_30MHZ) +#define OMAP_CK_MAX_RATE 30 +#elif defined(CONFIG_OMAP_ARM_60MHZ) +#define OMAP_CK_MAX_RATE 60 +#elif defined(CONFIG_OMAP_ARM_96MHZ) +#define OMAP_CK_MAX_RATE 96 +#elif defined(CONFIG_OMAP_ARM_120MHZ) +#define OMAP_CK_MAX_RATE 120 +#elif defined(CONFIG_OMAP_ARM_168MHZ) +#define OMAP_CK_MAX_RATE 168 +#elif defined(CONFIG_OMAP_ARM_182MHZ) +#define OMAP_CK_MAX_RATE 182 +#elif defined(CONFIG_OMAP_ARM_192MHZ) +#define OMAP_CK_MAX_RATE 192 +#elif defined(CONFIG_OMAP_ARM_195MHZ) +#define OMAP_CK_MAX_RATE 195 +#endif + +#define CK_DPLL_MASK 0x0fe0 + +/* Shared by CK and DSPC */ +#define MPUI_STROBE_MAX_1509 24 +#define MPUI_STROBE_MAX_1510 30 + +/* + * ---------------------------------------------------------------------------- + * Clock interface functions + * ---------------------------------------------------------------------------- + */ + +/* Clock initialization. */ +int init_ck(void); + +/* + * For some clocks you have a choice of which "parent" clocks they are derived + * from. Use this to select a "parent". See the platform documentation for + * valid combinations. + */ +int ck_can_set_input(ck_t); +int ck_set_input(ck_t ck, ck_t input); +int ck_get_input(ck_t ck, ck_t *input); + +/* + * Use this to set a clock rate. If other clocks are derived from this one, + * their rates will all change too. If this is a derived clock and I can't + * change it to match your request unless I also change the parent clock, then + * tough luck -- I won't change the parent automatically. I'll return an error + * if I can't get the clock within 10% of what you want. Otherwise I'll return + * the value I actually set it to. If I have to switch parents to get the rate + * then I will do this automatically (since it only affects this clock and its + * descendants). + */ +int ck_can_set_rate(ck_t); +int ck_set_rate(ck_t ck, int val_in_mhz); +int ck_get_rate(ck_t ck); + +/* + * Use this to get a bitmap of available rates for the clock. Caller allocates + * the buffer and passes in the length. Clock module fills up to len bytes of + * the buffer & passes back actual bytes used. + */ +int ck_get_rates(ck_t ck, void *buf, int len); +int ck_valid_rate(int rate); + +/* + * Idle a clock. What happens next depends on the clock ;). For example, if + * you idle the ARM_CK you might well end up in sleep mode on some platforms. + * If you try to idle a clock that doesn't support it I'll return an error. + * Note that idling a clock does not always take affect until certain h/w + * conditions are met. Consult the platform specs to learn more. + */ +int ck_can_idle(ck_t); +int ck_idle(ck_t); +int ck_activate(ck_t); +int ck_is_idle(ck_t); + +/* + * Enable/disable a clock. I'll return an error if the h/w doesn't support it. + * If you disable a clock being used by an active device then you probably + * just screwed it. YOU are responsible for making sure this doesn't happen. + */ +int ck_can_disable(ck_t); +int ck_enable(ck_t); +int ck_disable(ck_t); +int ck_is_enabled(ck_t); + +/* Enable/reset ARM peripherals (remove/set reset signal) */ +void ck_enable_peripherals(void); +void ck_reset_peripherals(void); + +/* Generate/clear a MPU or DSP reset */ +void ck_generate_reset(reset_t reset); +void ck_release_from_reset(reset_t reset); + +/* This gets a string representation of the clock's name. Useful for proc. */ +char *ck_get_name(ck_t); + +extern void start_mputimer1(unsigned long); + +#endif diff -Nru a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/dma.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,224 @@ +/* + * linux/include/asm-arm/arch-omap/dma.h + * + * Copyright (C) 2003 Nokia Corporation + * Author: Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define OMAP_LOGICAL_DMA_CH_COUNT 17 + +#define OMAP_DMA_NO_DEVICE 0 +#define OMAP_DMA_MCSI1_TX 1 +#define OMAP_DMA_MCSI1_RX 2 +#define OMAP_DMA_I2C_RX 3 +#define OMAP_DMA_I2C_TX 4 +#define OMAP_DMA_EXT_NDMA_REQ 5 +#define OMAP_DMA_EXT_NDMA_REQ2 6 +#define OMAP_DMA_UWIRE_TX 7 +#define OMAP_DMA_MCBSP1_DMA_TX 8 +#define OMAP_DMA_MCBSP1_DMA_RX 9 +#define OMAP_DMA_MCBSP3_DMA_TX 10 +#define OMAP_DMA_MCBSP3_DMA_RX 11 +#define OMAP_DMA_UART1_TX 12 +#define OMAP_DMA_UART1_RX 13 +#define OMAP_DMA_UART2_TX 14 +#define OMAP_DMA_UART2_RX 15 +#define OMAP_DMA_MCBSP2_TX 16 +#define OMAP_DMA_MCBSP2_RX 17 +#define OMAP_DMA_UART3_TX 18 +#define OMAP_DMA_UART3_RX 19 +#define OMAP_DMA_CAMERA_IF_RX 20 +#define OMAP_DMA_MMC_TX 21 +#define OMAP_DMA_MMC_RX 22 +#define OMAP_DMA_NAND 23 +#define OMAP_DMA_IRQ_LCD_LINE 24 +#define OMAP_DMA_MEMORY_STICK 25 +#define OMAP_DMA_USB_W2FC_RX0 26 +#define OMAP_DMA_USB_W2FC_RX1 27 +#define OMAP_DMA_USB_W2FC_RX2 28 +#define OMAP_DMA_USB_W2FC_TX0 29 +#define OMAP_DMA_USB_W2FC_TX1 30 +#define OMAP_DMA_USB_W2FC_TX2 31 + +/* These are only for 1610 */ +#define OMAP_DMA_CRYPTO_DES_IN 32 +#define OMAP_DMA_SPI_TX 33 +#define OMAP_DMA_SPI_RX 34 +#define OMAP_DMA_CRYPTO_HASH 35 +#define OMAP_DMA_CCP_ATTN 36 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 +#define OMAP_DMA_MMC2_TX 54 +#define OMAP_DMA_MMC2_RX 55 +#define OMAP_DMA_CRYPTO_DES_OUT 56 + + +#define OMAP_DMA_BASE 0xfffed800 +#define OMAP_DMA_GCR_REG (OMAP_DMA_BASE + 0x400) +#define OMAP_DMA_GSCR_REG (OMAP_DMA_BASE + 0x404) +#define OMAP_DMA_GRST_REG (OMAP_DMA_BASE + 0x408) +#define OMAP_DMA_HW_ID_REG (OMAP_DMA_BASE + 0x442) +#define OMAP_DMA_PCH2_ID_REG (OMAP_DMA_BASE + 0x444) +#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) +#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) +#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) +#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) +#define OMAP_DMA_CAPS_0_U_REG (OMAP_DMA_BASE + 0x44e) +#define OMAP_DMA_CAPS_0_L_REG (OMAP_DMA_BASE + 0x450) +#define OMAP_DMA_CAPS_1_U_REG (OMAP_DMA_BASE + 0x452) +#define OMAP_DMA_CAPS_1_L_REG (OMAP_DMA_BASE + 0x454) +#define OMAP_DMA_CAPS_2_REG (OMAP_DMA_BASE + 0x456) +#define OMAP_DMA_CAPS_3_REG (OMAP_DMA_BASE + 0x458) +#define OMAP_DMA_CAPS_4_REG (OMAP_DMA_BASE + 0x45a) +#define OMAP_DMA_PCH2_SR_REG (OMAP_DMA_BASE + 0x460) +#define OMAP_DMA_PCH0_SR_REG (OMAP_DMA_BASE + 0x480) +#define OMAP_DMA_PCH1_SR_REG (OMAP_DMA_BASE + 0x482) +#define OMAP_DMA_PCHD_SR_REG (OMAP_DMA_BASE + 0x4c0) + +#define OMAP1510_DMA_LCD_CTRL 0xfffedb00 +#define OMAP1510_DMA_LCD_TOP_F1_L 0xfffedb02 +#define OMAP1510_DMA_LCD_TOP_F1_U 0xfffedb04 +#define OMAP1510_DMA_LCD_BOT_F1_L 0xfffedb06 +#define OMAP1510_DMA_LCD_BOT_F1_U 0xfffedb08 + +#define OMAP1610_DMA_LCD_CSDP 0xfffee3c0 +#define OMAP1610_DMA_LCD_CCR 0xfffee3c2 +#define OMAP1610_DMA_LCD_CTRL 0xfffee3c4 +#define OMAP1610_DMA_LCD_TOP_B1_L 0xfffee3c8 +#define OMAP1610_DMA_LCD_TOP_B1_U 0xfffee3ca +#define OMAP1610_DMA_LCD_BOT_B1_L 0xfffee3cc +#define OMAP1610_DMA_LCD_BOT_B1_U 0xfffee3ce +#define OMAP1610_DMA_LCD_TOP_B2_L 0xfffee3d0 +#define OMAP1610_DMA_LCD_TOP_B2_U 0xfffee3d2 +#define OMAP1610_DMA_LCD_BOT_B2_L 0xfffee3d4 +#define OMAP1610_DMA_LCD_BOT_B2_U 0xfffee3d6 +#define OMAP1610_DMA_LCD_SRC_EI_B1 0xfffee3d8 +#define OMAP1610_DMA_LCD_SRC_FI_B1_L 0xfffee3da +#define OMAP1610_DMA_LCD_SRC_EN_B1 0xfffee3e0 +#define OMAP1610_DMA_LCD_SRC_FN_B1 0xfffee3e4 +#define OMAP1610_DMA_LCD_LCH_CTRL 0xfffee3ea +#define OMAP1610_DMA_LCD_SRC_FI_B1_U 0xfffee3f4 + + +/* Every LCh has its own set of the registers below */ +#define OMAP_DMA_CSDP_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00) +#define OMAP_DMA_CCR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02) +#define OMAP_DMA_CICR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04) +#define OMAP_DMA_CSR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06) +#define OMAP_DMA_CSSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08) +#define OMAP_DMA_CSSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a) +#define OMAP_DMA_CDSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c) +#define OMAP_DMA_CDSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e) +#define OMAP_DMA_CEN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10) +#define OMAP_DMA_CFN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12) +#define OMAP_DMA_CSFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14) +#define OMAP_DMA_CSEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16) +#define OMAP_DMA_CSAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18) +#define OMAP_DMA_CDAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a) +#define OMAP_DMA_CDEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c) +#define OMAP_DMA_CDFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e) +#define OMAP_DMA_COLOR_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20) +#define OMAP_DMA_COLOR_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22) +#define OMAP_DMA_CCR2_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24) +#define OMAP_DMA_CLNK_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28) +#define OMAP_DMA_LCH_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a) + +#define OMAP_DMA_TOUT_IRQ (1 << 0) +#define OMAP_DMA_DROP_IRQ (1 << 1) +#define OMAP_DMA_HALF_IRQ (1 << 2) +#define OMAP_DMA_FRAME_IRQ (1 << 3) +#define OMAP_DMA_LAST_IRQ (1 << 4) +#define OMAP_DMA_BLOCK_IRQ (1 << 5) +#define OMAP_DMA_SYNC_IRQ (1 << 6) + +#define OMAP_DMA_DATA_TYPE_S8 0x00 +#define OMAP_DMA_DATA_TYPE_S16 0x01 +#define OMAP_DMA_DATA_TYPE_S32 0x02 + +#define OMAP_DMA_SYNC_ELEMENT 0x00 +#define OMAP_DMA_SYNC_FRAME 0x01 +#define OMAP_DMA_SYNC_BLOCK 0x02 + +#define OMAP_DMA_PORT_EMIFF 0x00 +#define OMAP_DMA_PORT_EMIFS 0x01 +#define OMAP_DMA_PORT_OCP_T1 0x02 +#define OMAP_DMA_PORT_TIPB 0x03 +#define OMAP_DMA_PORT_OCP_T2 0x04 +#define OMAP_DMA_PORT_MPUI 0x05 + +#define OMAP_DMA_AMODE_CONSTANT 0x00 +#define OMAP_DMA_AMODE_POST_INC 0x01 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 + +/* LCD DMA block numbers */ +enum { + OMAP_LCD_DMA_B1_TOP, + OMAP_LCD_DMA_B1_BOTTOM, + OMAP_LCD_DMA_B2_TOP, + OMAP_LCD_DMA_B2_BOTTOM +}; + +extern int omap_request_dma(int dev_id, const char *dev_name, + void (* callback)(int lch, u16 ch_status, void *data), + void *data, int *dma_ch); +extern void omap_enable_dma_irq(int ch, u16 irq_bits); +extern void omap_disable_dma_irq(int ch, u16 irq_bits); +extern void omap_free_dma(int ch); +extern void omap_start_dma(int lch); +extern void omap_stop_dma(int lch); +extern void omap_set_dma_transfer_params(int lch, int data_type, + int elem_count, int frame_count, + int sync_mode); +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, + unsigned long src_start); +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, + unsigned long dest_start); + +/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ +extern int omap_dma_in_1510_mode(void); + +/* LCD DMA functions */ +extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), + void *data); +extern void omap_free_lcd_dma(void); +extern void omap_start_lcd_dma(void); +extern void omap_stop_lcd_dma(void); +extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, + int data_type); +extern void omap_set_lcd_dma_b1_rotation(int rotate); + +#endif /* __ASM_ARCH_DMA_H */ diff -Nru a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/fpga.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-omap/fpga.h + * + * Interrupt handler for OMAP-1510 FPGA + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_FPGA_H +#define __ASM_ARCH_OMAP_FPGA_H + +extern void fpga_init_irq(void); +extern unsigned char fpga_read(int reg); +extern void fpga_write(unsigned char val, int reg); + +#endif diff -Nru a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/gpio.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,68 @@ +/* + * linux/include/asm-arm/arch-omap/gpio.h + * + * OMAP GPIO handling defines and functions + * + * Copyright (C) 2003 Nokia Corporation + * + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_OMAP_GPIO_H +#define __ASM_ARCH_OMAP_GPIO_H + +#include +#include +#include + +#define OMAP_MPUIO_BASE 0xfffb5000 +#define OMAP_MPUIO_INPUT_LATCH 0x00 +#define OMAP_MPUIO_OUTPUT_REG 0x04 +#define OMAP_MPUIO_IO_CNTL 0x08 +#define OMAP_MPUIO_KBR_LATCH 0x10 +#define OMAP_MPUIO_KBC_REG 0x14 +#define OMAP_MPUIO_GPIO_EVENT_MODE_REG 0x18 +#define OMAP_MPUIO_GPIO_INT_EDGE_REG 0x1c +#define OMAP_MPUIO_KBD_INT 0x20 +#define OMAP_MPUIO_GPIO_INT 0x24 +#define OMAP_MPUIO_KBD_MASKIT 0x28 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c +#define OMAP_MPUIO_GPIO_DEBOUNCING_REG 0x30 +#define OMAP_MPUIO_LATCH_REG 0x34 + +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) + +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ + IH_MPUIO_BASE + ((nr) & 0x0f) : \ + IH_GPIO_BASE + ((nr) & 0x3f)) + +/* For EDGECTRL */ +#define OMAP_GPIO_NO_EDGE 0x00 +#define OMAP_GPIO_FALLING_EDGE 0x01 +#define OMAP_GPIO_RISING_EDGE 0x02 +#define OMAP_GPIO_BOTH_EDGES 0x03 + +extern int omap_request_gpio(int gpio); +extern void omap_free_gpio(int gpio); +extern void omap_set_gpio_direction(int gpio, int is_input); +extern void omap_set_gpio_dataout(int gpio, int enable); +extern int omap_get_gpio_datain(int gpio); +extern void omap_set_gpio_edge_ctrl(int gpio, int edge); + +#endif diff -Nru a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/hardware.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,327 @@ +/* + * linux/include/asm-arm/arch-omap/hardware.h + * + * Hardware definitions for TI OMAP processors and boards + * + * NOTE: Please put device driver specific defines into a separate header + * file for each driver. + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: RidgeRun, Inc. Greg Lonnon + * + * Reorganized for Linux-2.6 by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_HARDWARE_H +#define __ASM_ARCH_OMAP_HARDWARE_H + +#include +#include +#ifndef __ASSEMBLER__ +#include +#endif +#include + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_BASE 0xFFFB0000 /* Virtual */ +#define IO_SIZE 0x40000 +#define IO_START 0xFFFB0000 /* Physical */ + +#define PCIO_BASE 0 + +#define IO_ADDRESS(x) ((x)) + +/* + * --------------------------------------------------------------------------- + * Processor differentiation + * --------------------------------------------------------------------------- + */ + +#ifdef CONFIG_ARCH_OMAP730 +#include "omap730.h" +#define cpu_is_omap730() (1) +#else +#define cpu_is_omap730() (0) +#endif + +#ifdef CONFIG_ARCH_OMAP1510 +#include "omap1510.h" +#define cpu_is_omap1510() (1) +#else +#define cpu_is_omap1510() (0) +#endif + +#ifdef CONFIG_ARCH_OMAP1610 +#include "omap1610.h" +#define cpu_is_omap1610() (1) +#else +#define cpu_is_omap1610() (0) +#endif + +/* + * --------------------------------------------------------------------------- + * Board differentiation + * --------------------------------------------------------------------------- + */ + +#ifdef CONFIG_OMAP_INNOVATOR +#include "omap-innovator.h" +#define omap_is_innovator() (1) +#else +#define omap_is_innovator() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H2 +#include "omap-h2.h" +#define omap_is_h2() (1) +#else +#define omap_is_h2() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PERSEUS2 +#include "omap-perseus2.h" +#define omap_is_perseus2() (1) +#else +#define omap_is_perseus2() (0) +#endif + +/* + * --------------------------------------------------------------------------- + * Common definitions for all OMAP processors + * NOTE: Put all processor or board specific parts to the special header + * files. + * --------------------------------------------------------------------------- + */ + +/* + * ---------------------------------------------------------------------------- + * Base addresses + * ---------------------------------------------------------------------------- + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +#define OMAP_DSP_BASE 0xE0000000 +#define OMAP_DSP_SIZE 0x50000 +#define OMAP_DSP_START 0xE0000000 + +#define OMAP_DSPREG_BASE 0xE1000000 +#define OMAP_DSPREG_SIZE SZ_128K +#define OMAP_DSPREG_START 0xE1000000 + +/* + * ---------------------------------------------------------------------------- + * Clocks + * ---------------------------------------------------------------------------- + */ +#define CLKGEN_RESET_BASE (0xfffece00) +#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) +#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) +#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) +#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) +#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) +#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) +#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) + +#define CK_RATEF 1 +#define CK_IDLEF 2 +#define CK_ENABLEF 4 +#define CK_SELECTF 8 +#define SETARM_IDLE_SHIFT + +/* DPLL control registers */ +#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) +#define CK_DPLL1 (volatile __u16 *)(0xfffecf00) + +/* ULPD */ +#define ULPD_REG_BASE (0xfffe0800) +#define ULPD_IT_STATUS_REG (volatile __u16 *)(ULPD_REG_BASE + 0x14) +#define ULPD_CLOCK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x30) +#define ULPD_SOFT_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x34) +#define ULPD_DPLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x3c) +#define ULPD_STATUS_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x40) +#define ULPD_APLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x4c) +#define ULPD_POWER_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x50) +#define ULPD_CAM_CLK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x7c) + +/* + * --------------------------------------------------------------------------- + * Timers + * --------------------------------------------------------------------------- + */ +#define OMAP_32kHz_TIMER_BASE 0xfffb9000 + +/* 32k Timer Registers */ +#define TIMER32k_CR 0x08 +#define TIMER32k_TVR 0x00 +#define TIMER32k_TCR 0x04 + +/* 32k Timer Control Register definition */ +#define TIMER32k_TSS (1<<0) +#define TIMER32k_TRB (1<<1) +#define TIMER32k_INT (1<<2) +#define TIMER32k_ARL (1<<3) + +/* MPU Timer base addresses */ +#define OMAP_MPUTIMER_BASE 0xfffec500 +#define OMAP_MPUTIMER_OFF 0x00000100 + +#define OMAP_TIMER1_BASE 0xfffec500 +#define OMAP_TIMER2_BASE 0xfffec600 +#define OMAP_TIMER3_BASE 0xfffec700 +#define OMAP_WATCHDOG_BASE 0xfffec800 + +/* MPU Timer Registers */ +#define CNTL_TIMER 0 +#define LOAD_TIM 4 +#define READ_TIM 8 + +/* CNTL_TIMER register bits */ +#define MPUTIM_FREE (1<<6) +#define MPUTIM_CLOCK_ENABLE (1<<5) +#define MPUTIM_PTV_MASK (0x7< + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 + * are different. + */ + +#ifndef __ASM_ARCH_OMAP1510_IRQS_H +#define __ASM_ARCH_OMAP1510_IRQS_H + +/* + * IRQ numbers for interrupt handler 1 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + * + */ +#define INT_IH2_IRQ 0 +#define INT_CAMERA 1 +#define INT_FIQ 3 +#define INT_RTDX 6 +#define INT_DSP_MMU_ABORT 7 +#define INT_HOST 8 +#define INT_ABORT 9 +#define INT_DSP_MAILBOX1 10 +#define INT_DSP_MAILBOX2 11 +#define INT_BRIDGE_PRIV 13 +#define INT_GPIO_BANK1 14 +#define INT_UART3 15 +#define INT_TIMER3 16 +#define INT_DMA_CH0_6 19 +#define INT_DMA_CH1_7 20 +#define INT_DMA_CH2_8 21 +#define INT_DMA_CH3 22 +#define INT_DMA_CH4 23 +#define INT_DMA_CH5 24 +#define INT_DMA_LCD 25 +#define INT_TIMER1 26 +#define INT_WD_TIMER 27 +#define INT_BRIDGE_PUB 28 +#define INT_TIMER2 30 +#define INT_LCD_CTRL 31 + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1510_RES2 2 +#define INT_1510_SPI_TX 4 +#define INT_1510_SPI_RX 5 +#define INT_1510_RES12 12 +#define INT_1510_LB_MMU 17 +#define INT_1510_RES18 18 +#define INT_1510_LOCAL_BUS 29 + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1610_IH2_FIQ 2 +#define INT_1610_McBSP2_TX 4 +#define INT_1610_McBSP2_RX 5 +#define INT_1610_LCD_LINE 12 +#define INT_1610_GPTIMER1 17 +#define INT_1610_GPTIMER2 18 +#define INT_1610_SSR_FIFO_0 29 + +/* + * OMAP-730 specific IRQ numbers for interrupt handler 1 + */ +#define INT_730_IH2_FIQ 0 +#define INT_730_IH2_IRQ 1 +#define INT_730_USB_NON_ISO 2 +#define INT_730_USB_ISO 3 +#define INT_730_ICR 4 +#define INT_730_EAC 5 +#define INT_730_GPIO_BANK1 6 +#define INT_730_GPIO_BANK2 7 +#define INT_730_GPIO_BANK3 8 +#define INT_730_McBSP2TX 10 +#define INT_730_McBSP2RX 11 +#define INT_730_McBSP2RX_OVF 12 +#define INT_730_LCD_LINE 14 +#define INT_730_GSM_PROTECT 15 +#define INT_730_TIMER3 16 +#define INT_730_GPIO_BANK5 17 +#define INT_730_GPIO_BANK6 18 +#define INT_730_SPGIO_WR 29 + +/* + * IRQ numbers for interrupt handler 2 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + */ +#define IH2_BASE 32 + +#define INT_KEYBOARD (1 + IH2_BASE) +#define INT_uWireTX (2 + IH2_BASE) +#define INT_uWireRX (3 + IH2_BASE) +#define INT_I2C (4 + IH2_BASE) +#define INT_MPUIO (5 + IH2_BASE) +#define INT_USB_HHC_1 (6 + IH2_BASE) +#define INT_McBSP3TX (10 + IH2_BASE) +#define INT_McBSP3RX (11 + IH2_BASE) +#define INT_McBSP1TX (12 + IH2_BASE) +#define INT_McBSP1RX (13 + IH2_BASE) +#define INT_UART1 (14 + IH2_BASE) +#define INT_UART2 (15 + IH2_BASE) +#define INT_BT_MCSI1TX (16 + IH2_BASE) +#define INT_BT_MCSI1RX (17 + IH2_BASE) +#define INT_USB_W2FC (20 + IH2_BASE) +#define INT_1WIRE (21 + IH2_BASE) +#define INT_OS_TIMER (22 + IH2_BASE) +#define INT_MMC (23 + IH2_BASE) +#define INT_GAUGE_32K (24 + IH2_BASE) +#define INT_RTC_TIMER (25 + IH2_BASE) +#define INT_RTC_ALARM (26 + IH2_BASE) +#define INT_MEM_STICK (27 + IH2_BASE) +#define INT_DSP_MMU (28 + IH2_BASE) + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE) +#define INT_1510_COM_SPI_RO (31 + IH2_BASE) + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1610_FAC (0 + IH2_BASE) +#define INT_1610_USB_HHC_2 (7 + IH2_BASE) +#define INT_1610_USB_OTG (8 + IH2_BASE) +#define INT_1610_SoSSI (9 + IH2_BASE) +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) +#define INT_1610_MMC2 (42 + IH2_BASE) +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) +#define INT_1610_SPI (49 + IH2_BASE) +#define INT_1610_DMA_CH6 (53 + IH2_BASE) +#define INT_1610_DMA_CH7 (54 + IH2_BASE) +#define INT_1610_DMA_CH8 (55 + IH2_BASE) +#define INT_1610_DMA_CH9 (56 + IH2_BASE) +#define INT_1610_DMA_CH10 (57 + IH2_BASE) +#define INT_1610_DMA_CH11 (58 + IH2_BASE) +#define INT_1610_DMA_CH12 (59 + IH2_BASE) +#define INT_1610_DMA_CH13 (60 + IH2_BASE) +#define INT_1610_DMA_CH14 (61 + IH2_BASE) +#define INT_1610_DMA_CH15 (62 + IH2_BASE) +#define INT_1610_NAND (63 + IH2_BASE) + +/* + * OMAP-730 specific IRQ numbers for interrupt handler 2 + */ +#define INT_730_HW_ERRORS (0 + IH2_BASE) +#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) +#define INT_730_CFCD (2 + IH2_BASE) +#define INT_730_CFIREQ (3 + IH2_BASE) +#define INT_730_I2C (4 + IH2_BASE) +#define INT_730_PCC (5 + IH2_BASE) +#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) +#define INT_730_SPI_100K_1 (7 + IH2_BASE) +#define INT_730_SYREN_SPI (8 + IH2_BASE) +#define INT_730_VLYNQ (9 + IH2_BASE) +#define INT_730_GPIO_BANK4 (10 + IH2_BASE) +#define INT_730_McBSP1TX (11 + IH2_BASE) +#define INT_730_McBSP1RX (12 + IH2_BASE) +#define INT_730_McBSP1RX_OF (13 + IH2_BASE) +#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) +#define INT_730_UART_MODEM_1 (15 + IH2_BASE) +#define INT_730_MCSI (16 + IH2_BASE) +#define INT_730_uWireTX (17 + IH2_BASE) +#define INT_730_uWireRX (18 + IH2_BASE) +#define INT_730_SMC_CD (19 + IH2_BASE) +#define INT_730_SMC_IREQ (20 + IH2_BASE) +#define INT_730_HDQ_1WIRE (21 + IH2_BASE) +#define INT_730_TIMER32K (22 + IH2_BASE) +#define INT_730_MMC_SDIO (23 + IH2_BASE) +#define INT_730_UPLD (24 + IH2_BASE) +#define INT_730_RTC_TIMER (25 + IH2_BASE) +#define INT_730_RTC_ALARM (26 + IH2_BASE) +#define INT_730_USB_HHC_1 (27 + IH2_BASE) +#define INT_730_USB_HHC_2 (28 + IH2_BASE) +#define INT_730_USB_GENI (29 + IH2_BASE) +#define INT_730_USB_OTG (30 + IH2_BASE) +#define INT_730_CAMERA_IF (31 + IH2_BASE) +#define INT_730_RNG (32 + IH2_BASE) +#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) +#define INT_730_DBB_RF_EN (34 + IH2_BASE) +#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) +#define INT_730_SHA1_MD5 (36 + IH2_BASE) +#define INT_730_SPI_100K_2 (37 + IH2_BASE) +#define INT_730_RNG_IDLE (38 + IH2_BASE) +#define INT_730_MPUIO (39 + IH2_BASE) +#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) +#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) +#define INT_730_LLPC_OE_RISING (42 + IH2_BASE) +#define INT_730_LLPC_VSYNC (43 + IH2_BASE) +#define INT_730_WAKE_UP_REQ (46 + IH2_BASE) +#define INT_730_DMA_CH6 (53 + IH2_BASE) +#define INT_730_DMA_CH7 (54 + IH2_BASE) +#define INT_730_DMA_CH8 (55 + IH2_BASE) +#define INT_730_DMA_CH9 (56 + IH2_BASE) +#define INT_730_DMA_CH10 (57 + IH2_BASE) +#define INT_730_DMA_CH11 (58 + IH2_BASE) +#define INT_730_DMA_CH12 (59 + IH2_BASE) +#define INT_730_DMA_CH13 (60 + IH2_BASE) +#define INT_730_DMA_CH14 (61 + IH2_BASE) +#define INT_730_DMA_CH15 (62 + IH2_BASE) +#define INT_730_NAND (63 + IH2_BASE) + +/* OMAP-730 differences */ +#ifdef CONFIG_ARCH_OMAP730 +#undef INT_IH2_IRQ +#define INT_IH2_IRQ INT_730_IH2_IRQ +#undef INT_KEYBOARD +#define INT_KEYBOARD INT_730_MPUIO_KEYPAD +#undef INT_UART1 +#define INT_UART1 INT_730_UART_MODEM_1 +#undef INT_UART2 +#define INT_UART2 INT_730_UART_MODEM_IRDA_2 +#undef INT_MPUIO +#define INT_MPUIO INT_730_MPUIO +#undef INT_RTC_TIMER +#define INT_RTC_TIMER INT_730_RTC_TIMER +#undef INT_RTC_ALARM +#define INT_RTC_ALARM INT_730_RTC_ALARM +#endif + +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and + * 16 MPUIO lines */ +#define OMAP_MAX_GPIO_LINES 192 +#define IH_GPIO_BASE (128 + IH2_BASE) +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) +#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) + +#ifndef __ASSEMBLY__ +extern void omap_init_irq(void); +#endif + +/* + * The definition of NR_IRQS is in board-specific header file, which is + * included via hardware.h + */ +#include + +#endif diff -Nru a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/memory.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,92 @@ +/* + * linux/include/asm-arm/arch-omap/memory.h + * + * Memory map for OMAP-1510 and 1610 + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon + * + * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xbf000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (0x40000000) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xC0000000UL) +#define PHYS_OFFSET (0x10000000UL) + +/* + * OMAP-1510 Local Bus address offset + */ +#define OMAP1510_LB_OFFSET (0x30000000UL) + +/* + * The DRAM is contiguous. + */ +#define __virt_to_phys__is_a_macro +#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt__is_a_macro +#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET) + +/* + * Conversion between SDRAM and fake PCI bus, used by USB + * NOTE: Physical address must be converted to Local Bus address + * on OMAP-1510 only + */ +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro + +/* + * Bus address is physical address, except for OMAP-1510 Local Bus. + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +/* + * OMAP-1510 bus address is translated into a Local Bus address if the + * OMAP bus type is lbus. See dmadev_uses_omap_lbus(). + */ +#ifdef CONFIG_ARCH_OMAP1510 +#define bus_to_lbus(x) ((x) + (OMAP1510_LB_OFFSET - PHYS_OFFSET)) +#define lbus_to_bus(x) ((x) - (OMAP1510_LB_OFFSET - PHYS_OFFSET)) +#endif + +#define PHYS_TO_NID(addr) (0) +#endif + diff -Nru a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/mux.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,462 @@ +/* + * linux/include/asm-arm/arch-omap/mux.h + * + * Table of the Omap register configurations for the FUNC_MUX and + * PULL_DWN combinations. + * + * Copyright (C) 2003 Nokia Corporation + * + * Written by Tony Lindgren + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * NOTE: Please use the following naming style for new pin entries. + * For example, W8_1610_MMC2_DAT0, where: + * - W8 = ball + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 + * - MMC2_DAT0 = function + * + * Change log: + * Added entry for the I2C interface. (02Feb 2004) + * Copyright (C) 2004 Texas Instruments + * + * Added entry for the keypad and uwire CS1. (09Mar 2004) + * Copyright (C) 2004 Texas Instruments + * + */ + +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +#define PU_PD_SEL_NA 0 /* No pu_pd reg availabe */ + +#define DEBUG_MUX + +#ifdef DEBUG_MUX +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ + .mux_reg = FUNC_MUX_CTRL_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ + .pull_reg = PULL_DWN_CTRL_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ + .pu_pd_reg = PU_PD_SEL_##reg, \ + .pu_pd_val = status, + +#else + +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ + .mask_offset = mode_offset, \ + .mask = mode, + +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ + .pull_bit = bit, \ + .pull_val = status, + +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ + .pu_pd_val = status, + +#endif // DEBUG_MUX + +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ + pull_reg, pull_bit, pull_status, \ + pu_pd_reg, pu_pd_status, debug_status) \ +{ \ + .name = desc, \ + .debug = debug_status, \ + MUX_REG(mux_reg, mode_offset, mode) \ + PULL_REG(pull_reg, pull_bit, pull_status) \ + PU_PD_REG(pu_pd_reg, pu_pd_status) \ +}, + +#define PULL_DISABLED 0 +#define PULL_ENABLED 1 + +#define PULL_DOWN 0 +#define PULL_UP 1 + +typedef struct { + char *name; + unsigned char busy; + unsigned char debug; + + const char *mux_reg_name; + const unsigned int mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + + const char *pull_name; + const unsigned int pull_reg; + const unsigned char pull_val; + const unsigned char pull_bit; + + const char *pu_pd_name; + const unsigned int pu_pd_reg; + const unsigned char pu_pd_val; +} reg_cfg_set; + +/* + * Lookup table for FUNC_MUX and PULL_DWN register combinations for each + * device. See also reg_cfg_table below for the register values. + */ +typedef enum { + /* UART1 (BT_UART_GATING)*/ + UART1_TX = 0, + UART1_RTS, + + /* UART2 (COM_UART_GATING)*/ + UART2_TX, + UART2_RX, + UART2_CTS, + UART2_RTS, + + /* UART3 (GIGA_UART_GATING) */ + UART3_TX, + UART3_RX, + UART3_CTS, + UART3_RTS, + UART3_CLKREQ, + UART3_BCLK, /* 12MHz clock out */ + + /* USB master generic */ + R18_USB_VBUS, + R18_1510_USB_GPIO0, + W4_USB_PUEN, + W4_USB_CLKO, + + /* USB1 master */ + USB1_SUSP, + USB1_SEO, + USB1_TXEN, + USB1_TXD, + USB1_VP, + USB1_VM, + USB1_RCV, + USB1_SPEED, + + /* USB2 master */ + USB2_SUSP, + USB2_VP, + USB2_TXEN, + USB2_VM, + USB2_RCV, + USB2_SEO, + USB2_TXD, + + /* OMAP-1510 GPIO */ + R18_1510_GPIO0, + R19_1510_GPIO1, + M14_1510_GPIO2, + + /* MPUIO */ + MPUIO2, + MPUIO4, + MPUIO5, + T20_1610_MPUIO5, + W11_1610_MPUIO6, + V10_1610_MPUIO7, + W11_1610_MPUIO9, + V10_1610_MPUIO10, + W10_1610_MPUIO11, + E20_1610_MPUIO13, + U20_1610_MPUIO14, + E19_1610_MPUIO15, + + /* MCBSP2 */ + MCBSP2_CLKR, + MCBSP2_CLKX, + MCBSP2_DR, + MCBSP2_DX, + MCBSP2_FSR, + MCBSP2_FSX, + + /* MCBSP3 */ + MCBSP3_CLKX, + + /* Misc ballouts */ + BALLOUT_V8_ARMIO3, + + /* OMAP-1610 MMC2 */ + W8_1610_MMC2_DAT0, + V8_1610_MMC2_DAT1, + W15_1610_MMC2_DAT2, + R10_1610_MMC2_DAT3, + Y10_1610_MMC2_CLK, + Y8_1610_MMC2_CMD, + V9_1610_MMC2_CMDDIR, + V5_1610_MMC2_DATDIR0, + W19_1610_MMC2_DATDIR1, + R18_1610_MMC2_CLKIN, + + /* OMAP-1610 External Trace Interface */ + M19_1610_ETM_PSTAT0, + L15_1610_ETM_PSTAT1, + L18_1610_ETM_PSTAT2, + L19_1610_ETM_D0, + J19_1610_ETM_D6, + J18_1610_ETM_D7, + + /* OMAP-1610 GPIO */ + P20_1610_GPIO4, + V9_1610_GPIO7, + N19_1610_GPIO13, + P10_1610_GPIO22, + V5_1610_GPIO24, + AA20_1610_GPIO_41, + + /* OMAP-1610 uWire */ + V19_1610_UWIRE_SCLK, + U18_1610_UWIRE_SDI, + W21_1610_UWIRE_SDO, + N14_1610_UWIRE_CS0, + P15_1610_UWIRE_CS0, + N15_1610_UWIRE_CS1, + + /* First MMC */ + MMC_CMD, + MMC_DAT1, + MMC_DAT2, + MMC_DAT0, + MMC_CLK, + MMC_DAT3, + + /* OMAP-1610 USB0 alternate pin configuration */ + W9_USB0_TXEN, + AA9_USB0_VP, + Y5_USB0_RCV, + R9_USB0_VM, + V6_USB0_TXD, + W5_USB0_SE0, + V9_USB0_SPEED, + V9_USB0_SUSP, + + /* USB2 */ + W9_USB2_TXEN, + AA9_USB2_VP, + Y5_USB2_RCV, + R9_USB2_VM, + V6_USB2_TXD, + W5_USB2_SE0, + + /* UART1 1610 */ + + R13_1610_UART1_TX, + V14_1610_UART1_RX, + R14_1610_UART1_CTS, + AA15_1610_UART1_RTS, + + /* I2C OMAP-1610 */ + I2C_SCL, + I2C_SDA, + + /* Keypad */ + F18_1610_KBC0, + D20_1610_KBC1, + D19_1610_KBC2, + E18_1610_KBC3, + C21_1610_KBC4, + G18_1610_KBR0, + F19_1610_KBR1, + H14_1610_KBR2, + E20_1610_KBR3, + E19_1610_KBR4, + N19_1610_KBR5, + +} reg_cfg_t; + +#ifdef __MUX_C__ + +/* + * Table of various FUNC_MUX and PULL_DWN combinations for each device. + * See also reg_cfg_t above for the lookup table. + */ +static reg_cfg_set reg_cfg_table[] = { +/* + * description mux mode mux pull pull pull pu_pd pu dbg + * reg offset mode reg bit ena reg + */ +MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0) +MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0) + +/* UART2 (COM_UART_GATING), conflicts with USB2 */ +MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0) +MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0) +MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0) +MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0) + +/* UART3 (GIGA_UART_GATING) */ +MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0) +MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0) +MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0) +MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0) +MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0) +MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0) + +/* USB internal master generic */ +MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1) +MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1) +MUX_CFG("W4_USB_PUEN", D, 3, 0, 3, 5, 1, NA, 0, 1) +MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1) + +/* USB1 master */ +MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1) +MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1) +MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1) +MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1) +MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1) +MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1) +MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1) +MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1) + +/* USB2 master */ +MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1) +MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1) +MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1) +MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1) +MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1) +MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1) +MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1) + +/* OMAP-1510 GPIO */ +MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1) +MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1) +MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1) + +/* MPUIO */ +MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1) +MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1) +MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1) + +MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1) +MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1) +MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1) +MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1) +MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1) +MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1) +MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1) +MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1) +MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1) + +/* MCBSP2 */ +MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1) +MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1) +MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1) +MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1) +MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1) +MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1) + +/* MCBSP3 NOTE: Mode must 1 for clock */ +MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1) + +/* Misc ballouts */ +MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1) + +/* OMAP-1610 MMC2 */ +MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1) +MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1) +MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1) +MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1) +MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1) +MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1) +MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1) +MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1) +MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1) +MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1) + +/* OMAP-1610 External Trace Interface */ +MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1) +MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1) +MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1) +MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1) +MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1) +MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1) + +/* OMAP-1610 GPIO */ +MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1) +MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1) +MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1) +MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1) +MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1) +MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1) + +/* OMAP-1610 uWire */ +MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1) +MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1) +MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1) +MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1) +MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) +MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 0, 0, 0, 0, 0, 0) + +/* First MMC interface, same on 1510 and 1610 */ +MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1) +MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1) +MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1) +MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1) +MUX_CFG("MMC_CLK", A, 21, 0, 0, 0, 0, 0, 0, 1) +MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1) + +/* OMAP-1610 USB0 alternate configuration */ +MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1) +MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1) +MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1) +MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1) +MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1) +MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1) +MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1) +MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1) + +/* USB2 interface */ +MUX_CFG("W9_USB2_TXEN", B, 9, 1, 0, 0, 0, NA, 0, 1) +MUX_CFG("AA9_USB2_VP", B, 6, 1, 0, 0, 0, NA, 0, 1) +MUX_CFG("Y5_USB2_RCV", C, 21, 1, 0, 0, 0, NA, 0, 1) +MUX_CFG("R8_USB2_VM", C, 18, 1, 0, 0, 0, NA, 0, 1) +MUX_CFG("V6_USB2_TXD", C, 27, 2, 0, 0, 0, NA, 0, 1) +MUX_CFG("W5_USB2_SE0", C, 24, 2, 0, 0, 0, NA, 0, 1) + + +/* UART1 */ +MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1) +MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1) +MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1) +MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1) + +/* I2C interface */ +MUX_CFG("I2C_SCL", 7, 24, 0, 0, 0, 0, 0, 0, 0) +MUX_CFG("I2C_SDA", 7, 27, 0, 0, 0, 0, 0, 0, 0) + +/* Keypad */ +MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0) +MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0) +MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0) +MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0) +MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0) +MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0) +MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0) +MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0) +MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0) +MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0) +MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0) + +}; + +#endif /* __MUX_C__ */ + +extern int omap_cfg_reg(reg_cfg_t reg_cfg); + +#endif diff -Nru a/include/asm-arm/arch-omap/omap-h2.h b/include/asm-arm/arch-omap/omap-h2.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap-h2.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/omap-h2.h + * + * Hardware definitions for TI OMAP1610 H2 board. + * + * Cleanup for Linux-2.6 by Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_H2_H +#define __ASM_ARCH_OMAP_H2_H + +/* Placeholder for H2 specific defines */ + +#endif /* __ASM_ARCH_OMAP_H2_H */ + diff -Nru a/include/asm-arm/arch-omap/omap-innovator.h b/include/asm-arm/arch-omap/omap-innovator.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap-innovator.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,214 @@ +/* + * linux/include/asm-arm/arch-omap/omap-innovator.h + * + * Copyright (C) 2001 RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_OMAP_INNOVATOR_H +#define __ASM_ARCH_OMAP_INNOVATOR_H + +#if defined (CONFIG_ARCH_OMAP1510) + +/* + * --------------------------------------------------------------------------- + * OMAP-1510 FPGA + * --------------------------------------------------------------------------- + */ +#define OMAP1510P1_FPGA_BASE 0xE8000000 /* Virtual */ +#define OMAP1510P1_FPGA_SIZE SZ_4K +#define OMAP1510P1_FPGA_START 0x08000000 /* Physical */ + +/* Revision */ +#define OMAP1510P1_FPGA_REV_LOW (OMAP1510P1_FPGA_BASE + 0x0) +#define OMAP1510P1_FPGA_REV_HIGH (OMAP1510P1_FPGA_BASE + 0x1) + +#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2) +#define OMAP1510P1_FPGA_LED_DIGIT (OMAP1510P1_FPGA_BASE + 0x3) +#define INNOVATOR_FPGA_HID_SPI (OMAP1510P1_FPGA_BASE + 0x4) +#define OMAP1510P1_FPGA_POWER (OMAP1510P1_FPGA_BASE + 0x5) + +/* Interrupt status */ +#define OMAP1510P1_FPGA_ISR_LO (OMAP1510P1_FPGA_BASE + 0x6) +#define OMAP1510P1_FPGA_ISR_HI (OMAP1510P1_FPGA_BASE + 0x7) + +/* Interrupt mask */ +#define OMAP1510P1_FPGA_IMR_LO (OMAP1510P1_FPGA_BASE + 0x8) +#define OMAP1510P1_FPGA_IMR_HI (OMAP1510P1_FPGA_BASE + 0x9) + +/* Reset registers */ +#define OMAP1510P1_FPGA_HOST_RESET (OMAP1510P1_FPGA_BASE + 0xa) +#define OMAP1510P1_FPGA_RST (OMAP1510P1_FPGA_BASE + 0xb) + +#define OMAP1510P1_FPGA_AUDIO (OMAP1510P1_FPGA_BASE + 0xc) +#define OMAP1510P1_FPGA_DIP (OMAP1510P1_FPGA_BASE + 0xe) +#define OMAP1510P1_FPGA_FPGA_IO (OMAP1510P1_FPGA_BASE + 0xf) +#define OMAP1510P1_FPGA_UART1 (OMAP1510P1_FPGA_BASE + 0x14) +#define OMAP1510P1_FPGA_UART2 (OMAP1510P1_FPGA_BASE + 0x15) +#define OMAP1510P1_FPGA_OMAP1510_STATUS (OMAP1510P1_FPGA_BASE + 0x16) +#define OMAP1510P1_FPGA_BOARD_REV (OMAP1510P1_FPGA_BASE + 0x18) +#define OMAP1510P1_PPT_DATA (OMAP1510P1_FPGA_BASE + 0x100) +#define OMAP1510P1_PPT_STATUS (OMAP1510P1_FPGA_BASE + 0x101) +#define OMAP1510P1_PPT_CONTROL (OMAP1510P1_FPGA_BASE + 0x102) + +#define OMAP1510P1_FPGA_TOUCHSCREEN (OMAP1510P1_FPGA_BASE + 0x204) + +#define INNOVATOR_FPGA_INFO (OMAP1510P1_FPGA_BASE + 0x205) +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510P1_FPGA_BASE + 0x206) +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510P1_FPGA_BASE + 0x207) +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510P1_FPGA_BASE + 0x208) +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510P1_FPGA_BASE + 0x209) +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510P1_FPGA_BASE + 0x20a) +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510P1_FPGA_BASE + 0x20b) +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510P1_FPGA_BASE + 0x20c) +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510P1_FPGA_BASE + 0x20d) +#define INNOVATOR_FPGA_ISR2 (OMAP1510P1_FPGA_BASE + 0x20e) +#define INNOVATOR_FPGA_IMR2 (OMAP1510P1_FPGA_BASE + 0x210) + +#define OMAP1510P1_FPGA_ETHR_START (OMAP1510P1_FPGA_START + 0x300) +#define OMAP1510P1_FPGA_ETHR_BASE (OMAP1510P1_FPGA_BASE + 0x300) + +/* + * Power up Giga UART driver, turn on HID clock. + * Turn off BT power, since we're not using it and it + * draws power. + */ +#define OMAP1510P1_FPGA_RESET_VALUE 0x42 + +#define OMAP1510P1_FPGA_PCR_IF_PD0 (1 << 7) +#define OMAP1510P1_FPGA_PCR_COM2_EN (1 << 6) +#define OMAP1510P1_FPGA_PCR_COM1_EN (1 << 5) +#define OMAP1510P1_FPGA_PCR_EXP_PD0 (1 << 4) +#define OMAP1510P1_FPGA_PCR_EXP_PD1 (1 << 3) +#define OMAP1510P1_FPGA_PCR_48MHZ_CLK (1 << 2) +#define OMAP1510P1_FPGA_PCR_4MHZ_CLK (1 << 1) +#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0 (1 << 0) + +/* + * Innovator/OMAP1510 FPGA HID register bit definitions + */ +#define FPGA_HID_SCLK (1<<0) /* output */ +#define FPGA_HID_MOSI (1<<1) /* output */ +#define FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ +#define FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ +#define FPGA_HID_MISO (1<<4) /* input */ +#define FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ +#define FPGA_HID_rsrvd (1<<6) +#define FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ + +#ifndef OMAP_SDRAM_DEVICE +#define OMAP_SDRAM_DEVICE D256M_1X16_4B +#endif + +#define OMAP1510P1_IMIF_PRI_VALUE 0x00 +#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 +#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 + +/* + * These definitions define an area of FLASH set aside + * for the use of MTD/JFFS2. This is the area of flash + * that a JFFS2 filesystem will reside which is mounted + * at boot with the "root=/dev/mtdblock/0 rw" + * command line option. The flash address used here must + * fall within the legal range defined by rrload for storing + * the filesystem component. This address will be sufficiently + * deep into the overall flash range to avoid the other + * components also stored in flash such as the bootloader, + * the bootloader params, and the kernel. + * The SW2 settings for the map below are: + * 1 off, 2 off, 3 on, 4 off. + */ + +/* Intel flash_0, partitioned as expected by rrload */ +#define OMAP_FLASH_0_BASE 0xD8000000 +#define OMAP_FLASH_0_START 0x00000000 +#define OMAP_FLASH_0_SIZE SZ_16M + +/* Intel flash_1, used for cramfs or other flash file systems */ +#define OMAP_FLASH_1_BASE 0xD9000000 +#define OMAP_FLASH_1_START 0x01000000 +#define OMAP_FLASH_1_SIZE SZ_16M + +/* The FPGA IRQ is cascaded through GPIO_13 */ +#define INT_FPGA (IH_GPIO_BASE + 13) + +/* IRQ Numbers for interrupts muxed through the FPGA */ +#define IH_FPGA_BASE IH_BOARD_BASE +#define INT_FPGA_ATN (IH_FPGA_BASE + 0) +#define INT_FPGA_ACK (IH_FPGA_BASE + 1) +#define INT_FPGA2 (IH_FPGA_BASE + 2) +#define INT_FPGA3 (IH_FPGA_BASE + 3) +#define INT_FPGA4 (IH_FPGA_BASE + 4) +#define INT_FPGA5 (IH_FPGA_BASE + 5) +#define INT_FPGA6 (IH_FPGA_BASE + 6) +#define INT_FPGA7 (IH_FPGA_BASE + 7) +#define INT_FPGA8 (IH_FPGA_BASE + 8) +#define INT_FPGA9 (IH_FPGA_BASE + 9) +#define INT_FPGA10 (IH_FPGA_BASE + 10) +#define INT_FPGA11 (IH_FPGA_BASE + 11) +#define INT_FPGA12 (IH_FPGA_BASE + 12) +#define INT_ETHER (IH_FPGA_BASE + 13) +#define INT_FPGAUART1 (IH_FPGA_BASE + 14) +#define INT_FPGAUART2 (IH_FPGA_BASE + 15) +#define INT_FPGA_TS (IH_FPGA_BASE + 16) +#define INT_FPGA17 (IH_FPGA_BASE + 17) +#define INT_FPGA_CAM (IH_FPGA_BASE + 18) +#define INT_FPGA_RTC_A (IH_FPGA_BASE + 19) +#define INT_FPGA_RTC_B (IH_FPGA_BASE + 20) +#define INT_FPGA_CD (IH_FPGA_BASE + 21) +#define INT_FPGA22 (IH_FPGA_BASE + 22) +#define INT_FPGA23 (IH_FPGA_BASE + 23) + +#define NR_FPGA_IRQS 24 + +#define MAXIRQNUM (IH_FPGA_BASE + NR_FPGA_IRQS - 1) +#define MAXFIQNUM MAXIRQNUM +#define MAXSWINUM MAXIRQNUM + +#define NR_IRQS 256 + +#ifndef __ASSEMBLY__ +void fpga_write(unsigned char val, int reg); +unsigned char fpga_read(int reg); +#endif + +#elif defined (CONFIG_ARCH_OMAP1610) + +/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ +#define OMAP1610_ETHR_BASE 0xE8000000 +#define OMAP1610_ETHR_SIZE SZ_4K +#define OMAP1610_ETHR_START 0x04000000 + +/* Intel STRATA NOR flash at CS3 */ +#define OMAP1610_NOR_FLASH_BASE 0xD8000000 +#define OMAP1610_NOR_FLASH_SIZE SZ_32M +#define OMAP1610_NOR_FLASH_START 0x0C000000 + +#define MAXIRQNUM (IH_BOARD_BASE) +#define MAXFIQNUM MAXIRQNUM +#define MAXSWINUM MAXIRQNUM + +#define NR_IRQS (MAXIRQNUM + 1) + +#else +#error "Only OMAP1510 and OMAP1610 Innovator supported!" +#endif +#endif diff -Nru a/include/asm-arm/arch-omap/omap-perseus2.h b/include/asm-arm/arch-omap/omap-perseus2.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap-perseus2.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,152 @@ +/* + * linux/include/asm-arm/arch-omap/omap-perseus2.h + * + * Copyright 2003 by Texas Instruments Incorporated + * OMAP730 / P2-sample additions + * Author: Jean Pihet + * + * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) + * Author: RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H +#define __ASM_ARCH_OMAP_P2SAMPLE_H + +#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2) + +/* + * NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER + * P2SAMPLE_ since they are specific to the EVM and not the chip. + */ + +/* --------------------------------------------------------------------------- + * OMAP730 Debug Board FPGA + * --------------------------------------------------------------------------- + * + */ + +/* maps in the FPGA registers and the ETHR registers */ +#define OMAP730_FPGA_BASE 0xE8000000 /* VA */ +#define OMAP730_FPGA_SIZE SZ_4K /* SIZE */ +#define OMAP730_FPGA_START 0x04000000 /* PA */ + +#define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START +#define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE +#define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */ +#define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */ +#define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */ +#define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */ +#define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */ +#define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */ +#define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */ + +// LEDs definition on debug board (16 LEDs) +#define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15) +#define OMAP730_FPGA_LED_STARTSTOP (1 << 14) +#define OMAP730_FPGA_LED_HALTED (1 << 13) +#define OMAP730_FPGA_LED_IDLE (1 << 12) +#define OMAP730_FPGA_LED_TIMER (1 << 11) +// cpu0 load-meter LEDs +#define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... +#define OMAP730_FPGA_LOAD_METER_SIZE 11 +#define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1) + +#ifndef OMAP_SDRAM_DEVICE +#define OMAP_SDRAM_DEVICE D256M_1X16_4B +#endif + + +/* + * These definitions define an area of FLASH set aside + * for the use of MTD/JFFS2. This is the area of flash + * that a JFFS2 filesystem will reside which is mounted + * at boot with the "root=/dev/mtdblock/0 rw" + * command line option. + */ + +/* Intel flash_0, partitioned as expected by rrload */ +#define OMAP_FLASH_0_BASE 0xD8000000 /* VA */ +#define OMAP_FLASH_0_START 0x00000000 /* PA */ +#define OMAP_FLASH_0_SIZE SZ_32M + +/* 2.9.6 Traffic Controller Memory Interface Registers */ +#define OMAP_FLASH_CFG_0 0xfffecc10 +#define OMAP_FLASH_ACFG_0 0xfffecc50 + +#define OMAP_FLASH_CFG_1 0xfffecc14 +#define OMAP_FLASH_ACFG_1 0xfffecc54 + +/* + * Configuration Registers + */ +#define PERSEUS2_CONFIG_BASE 0xfffe1000 +#define PERSEUS2_IO_CONF_0 0xfffe1070 +#define PERSEUS2_IO_CONF_1 0xfffe1074 +#define PERSEUS2_IO_CONF_2 0xfffe1078 +#define PERSEUS2_IO_CONF_3 0xfffe107c +#define PERSEUS2_IO_CONF_4 0xfffe1080 +#define PERSEUS2_IO_CONF_5 0xfffe1084 +#define PERSEUS2_IO_CONF_6 0xfffe1088 +#define PERSEUS2_IO_CONF_7 0xfffe108c +#define PERSEUS2_IO_CONF_8 0xfffe1090 +#define PERSEUS2_IO_CONF_9 0xfffe1094 +#define PERSEUS2_IO_CONF_10 0xfffe1098 +#define PERSEUS2_IO_CONF_11 0xfffe109c +#define PERSEUS2_IO_CONF_12 0xfffe10a0 +#define PERSEUS2_IO_CONF_13 0xfffe10a4 + +#define PERSEUS2_MODE_1 0xfffe1010 +#define PERSEUS2_MODE_2 0xfffe1014 + +/* CSMI specials: in terms of base + offset */ +#define PERSEUS2_MODE2_OFFSET 0x14 + +/* DSP control: ICR registers */ +#define ICR_BASE 0xfffbb800 +/* M_CTL */ +#define DSP_M_CTL ((volatile __u16 *)0xfffbb804) +/* DSP control: MMU registers */ +#define DSP_MMU_BASE ((volatile __u16 *)0xfffed200) + +/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */ +#define INT_ETHER INT_730_MPU_EXT_NIRQ + +#define MAXIRQNUM IH_BOARD_BASE +#define MAXFIQNUM MAXIRQNUM +#define MAXSWINUM MAXIRQNUM + +#define NR_IRQS (MAXIRQNUM + 1) + +#ifndef __ASSEMBLY__ +void fpga_write(unsigned char val, int reg); +unsigned char fpga_read(int reg); +#endif + +/* PCC_UPLD control register: OMAP730 */ +#define PCC_UPLD_CTRL_REG_BASE (0xfffe0900) +#define PCC_UPLD_CTRL_REG (volatile __u16 *)(PCC_UPLD_CTRL_REG_BASE + 0x00) + +#else +#error "Only OMAP730 Perseus2 supported!" +#endif + +#endif diff -Nru a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap1510.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,54 @@ +/* linux/include/asm-arm/arch-omap/omap1510.h + * + * Hardware definitions for TI OMAP1510 processor. + * + * Cleanup for Linux-2.6 by Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP1510_H +#define __ASM_ARCH_OMAP1510_H + +/* + * ---------------------------------------------------------------------------- + * Base addresses + * ---------------------------------------------------------------------------- + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +#define OMAP_SRAM_BASE 0xD0000000 +#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K) +#define OMAP_SRAM_START 0x20000000 + +#define OMAP_MCBSP1_BASE 0xE1011000 +#define OMAP_MCBSP1_SIZE SZ_4K +#define OMAP_MCBSP1_START 0xE1011000 + +#define OMAP_MCBSP2_BASE 0xFFFB1000 + +#define OMAP_MCBSP3_BASE 0xE1017000 +#define OMAP_MCBSP3_SIZE SZ_4K +#define OMAP_MCBSP3_START 0xE1017000 + +#endif /* __ASM_ARCH_OMAP1510_H */ + diff -Nru a/include/asm-arm/arch-omap/omap1610.h b/include/asm-arm/arch-omap/omap1610.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap1610.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,73 @@ +/* linux/include/asm-arm/arch-omap/omap1610.h + * + * Hardware definitions for TI OMAP1610 processor. + * + * Cleanup for Linux-2.6 by Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP1610_H +#define __ASM_ARCH_OMAP1610_H + +/* + * ---------------------------------------------------------------------------- + * Base addresses + * ---------------------------------------------------------------------------- + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +#define OMAP_SRAM_BASE 0xD0000000 +#define OMAP_SRAM_SIZE (SZ_16K) +#define OMAP_SRAM_START 0x20000000 + +/* + * ---------------------------------------------------------------------------- + * System control registers + * ---------------------------------------------------------------------------- + */ + +#define OMAP_RESET_CONTROL 0xfffe1140 +#define ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24) +#define CONF_VOLTAGE_CTRL_0 0xfffe1060 +#define CONF_VOLTAGE_VDDSHV6 (1 << 8) +#define CONF_VOLTAGE_VDDSHV7 (1 << 9) +#define CONF_VOLTAGE_VDDSHV8 (1 << 10) +#define CONF_VOLTAGE_VDDSHV9 (1 << 11) +#define SUBLVDS_CONF_VALID (1 << 13) + +/* + * --------------------------------------------------------------------------- + * TIPB bus interface + * --------------------------------------------------------------------------- + */ + +#define OMAP_TIPB_SWITCH 0xfffbc800 +#define TIPB_BRIDGE_INT 0xfffeca00 /* Private TIPB_CNTL */ +#define PRIVATE_MPU_TIPB_CNTL 0xfffeca08 +#define TIPB_BRIDGE_EXT 0xfffed300 /* Public (Shared) TIPB_CNTL */ +#define PUBLIC_MPU_TIPB_CNTL 0xfffed308 +#define TIPB_SWITCH_CFG OMAP_TIPB_SWITCH +#define MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_CFG + 0x160) + +#endif /* __ASM_ARCH_OMAP1610_H */ + diff -Nru a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/omap730.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,50 @@ +/* linux/include/asm-arm/arch-omap/omap730.h + * + * Hardware definitions for TI OMAP730 processor. + * + * Cleanup for Linux-2.6 by Dirk Behme + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP730_H +#define __ASM_ARCH_OMAP730_H + +/* + * ---------------------------------------------------------------------------- + * Base addresses + * ---------------------------------------------------------------------------- + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +#define OMAP_SRAM_BASE 0xD0000000 +#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K) +#define OMAP_SRAM_START 0x20000000 + +#define OMAP_MCBSP1_BASE 0xfffb1000 +#define OMAP_MCBSP1_SIZE (SZ_1K * 2) +#define OMAP_MCBSP1_START 0xfffb1000 + +#define OMAP_MCBSP2_BASE 0xfffb1800 + +#endif /* __ASM_ARCH_OMAP730_H */ + diff -Nru a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/param.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,24 @@ +/* + * linux/include/asm-arm/arch-omap/param.h + * + * Initially based on linux/include/asm-arm/arch-integrator/param.h + * Copyright (C) 1999 ARM Limited + * + * BRIEF MODULE DESCRIPTION + * a place holder + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + diff -Nru a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/pm.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,150 @@ +/* + * FILE NAME include/asm/arch-omap/pm.h + * + * BRIEF MODULE DESCRIPTION + * + * Author: MontaVista Software, Inc. + * support@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * List of global OMAP registers to preserve. All registers are 16 bits + * and must be accessed with 16 read/writes. + * More ones like CP and general purpose register values are preserved + * with the stack pointer in sleep.S. + */ +#ifndef __ASM_ARCH_OMAP1510_PM_H +#define __ASM_ARCH_OMAP1510_PM_H + +#define ARM_REG_BASE (0xfffece00) +#define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4) +#define ARM_ASM_IDLECT2 (ARM_REG_BASE + 0x8) +#define ARM_ASM_RSTCT1 (ARM_REG_BASE + 0x10) +#define ARM_ASM_RSTCT2 (ARM_REG_BASE + 0x14) +#define ARM_ASM_SYSST (ARM_REG_BASE + 0x18) +/* + * Traffic Controller Memory Interface Registers + */ +#define TCMIF_BASE 0xfffecc00 +#define EMIFS_ASM_CONFIG_REG (TCMIF_BASE + 0x0c) +#define EMIFF_ASM_SDRAM_CONFIG (TCMIF_BASE + 0x20) +#define IRQ_MIR1 (volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR) +#define IRQ_MIR2 (volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR) + +#define IDLE_WAIT_CYCLES 0x000000ff +#define PERIPHERAL_ENABLE 0x2 +#define BIG_SLEEP_REQUEST 0x0cc5 +#define IDLE_LOOP_REQUEST 0x0c00 +#define SELF_REFRESH_MODE 0x0c000001 +#define IDLE_EMIFS_REQUEST 0xc +#define IDLE_CLOCK_DOMAINS 0x2 +#define MODEM_32K_EN 0x1 + +#ifndef __ASSEMBLER__ +extern void omap1510_pm_idle(void); +extern void omap_pm_suspend(void); +extern int omap1510_cpu_suspend(void); +extern int omap1510_idle_loop_suspend(void); +extern struct async_struct *omap_pm_sercons; +extern unsigned int serial_in(struct async_struct *, int); +extern unsigned int serial_out(struct async_struct *, int, int); + +#define OMAP1510_SRAM_IDLE_SUSPEND 0xd002F000 +#define OMAP1510_SRAM_API_SUSPEND 0xd002F200 +#define CPU_SUSPEND_SIZE 200 +#define ARM_REG_BASE (0xfffece00) +#define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4) +#define ARM_ASM_IDLECT2 (ARM_REG_BASE + 0x8) +#define ARM_ASM_RSTCT1 (ARM_REG_BASE + 0x10) +#define ARM_ASM_RSTCT2 (ARM_REG_BASE + 0x14) +#define ARM_ASM_SYSST (ARM_REG_BASE + 0x18) + +#define TCMIF_BASE 0xfffecc00 +#define PM_EMIFS_CONFIG_REG (volatile unsigned int *)(TCMIF_BASE + 0x0c) +#define PM_EMIFF_SDRAM_CONFIG (volatile unsigned int *)(TCMIF_BASE + 0x20) + +#define ULPD_LOW_POWER_REQ 0x3 + +#define DSP_IDLE_DELAY 10 +#define DSP_IDLE 0x0040 +#define DSP_ENABLE 0x0002 +#define SUFFICIENT_DSP_RESET_TIME 1000 +#define DEFAULT_MPUI_CONFIG 0x05cf +#define ENABLE_XORCLK 0x2 +#define DSP_RESET 0x2000 +#define TC_IDLE_REQUEST (0x0000000c) +#define EMIFF_CONFIG_REG EMIFF_SDRAM_CONFIG + + +#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x +#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x] +#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] + +#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x +#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] +#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] + +#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x +#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x] +#define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x] + +enum arm_save_state { + ARM_SLEEP_SAVE_START = 0, + /* + * 9 MPU control registers, all 16 bits + */ + ARM_SLEEP_SAVE_ARM_CKCTL, ARM_SLEEP_SAVE_ARM_IDLECT1, + ARM_SLEEP_SAVE_ARM_IDLECT2, ARM_SLEEP_SAVE_ARM_EWUPCT, + ARM_SLEEP_SAVE_ARM_RSTCT1, ARM_SLEEP_SAVE_ARM_RSTCT2, + ARM_SLEEP_SAVE_ARM_SYSST, + + ARM_SLEEP_SAVE_SIZE +}; + +enum ulpd_save_state { + ULDP_SLEEP_SAVE_START = 0, + ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG, + ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG, + ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG, + ULPD_SLEEP_SAVE_SIZE +}; + +enum mpui_save_state { + /* + * MPUI registers 32 bits + */ + MPUI_SLEEP_SAVE_MPUI_CTRL_REG, MPUI_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, + MPUI_SLEEP_SAVE_MPUI_DSP_API_CONFIG, + MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG, + MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG, + MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG, + MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2, + + MPUI_SLEEP_SAVE_SIZE +}; + + +#endif /* ASSEMBLER */ +#endif diff -Nru a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/serial.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,167 @@ +/* + * linux/include/asm-arm/arch-omap/serial.h + * + * BRIEF MODULE DESCRIPTION + * serial definitions + * + */ + +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + + +#define OMAP1510_UART1_BASE (unsigned char *)0xfffb0000 +#define OMAP1510_UART2_BASE (unsigned char *)0xfffb0800 +#define OMAP1510_UART3_BASE (unsigned char *)0xfffb9800 + +#define OMAP730_UART1_BASE (unsigned char *)0xfffb0000 +#define OMAP730_UART2_BASE (unsigned char *)0xfffb0800 + +#if defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP1610) +#define OMAP_SERIAL_REG_SHIFT 2 +#else +#define OMAP_SERIAL_REG_SHIFT 0 +#endif + + +#ifndef __ASSEMBLY__ + +#include +#include + + +/* UART3 Registers Maping through MPU bus */ +#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ +#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) +#define UART3_THR (OMAP_MPU_UART3_BASE + 0) +#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) +#define UART3_IER (OMAP_MPU_UART3_BASE + 4) +#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) +#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) +#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) +#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) +#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) +#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) +#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) +#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) +#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) +#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) +#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) +#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) +#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) + +#ifdef CONFIG_ARCH_OMAP1510 +#define BASE_BAUD (12000000/16) +#endif + +#ifdef CONFIG_ARCH_OMAP1610 +#define BASE_BAUD (48000000/16) +#endif + +#ifdef CONFIG_ARCH_OMAP730 +#define BASE_BAUD (48000000/16) + +#define RS_TABLE_SIZE 2 + +#define STD_COM_FLAGS (ASYNC_SKIP_TEST) + +#define STD_SERIAL_PORT_DEFNS \ + { \ + .uart = PORT_OMAP, \ + .baud_base = BASE_BAUD, \ + .iomem_base = OMAP730_UART1_BASE, \ + .iomem_reg_shift = 0, \ + .io_type = SERIAL_IO_MEM, \ + .irq = INT_UART1, \ + .flags = STD_COM_FLAGS, \ + }, { \ + .uart = PORT_OMAP, \ + .baud_base = BASE_BAUD, \ + .iomem_base = OMAP730_UART2_BASE, \ + .iomem_reg_shift = 0, \ + .io_type = SERIAL_IO_MEM, \ + .irq = INT_UART2, \ + .flags = STD_COM_FLAGS, \ + } + +#else + +#define RS_TABLE_SIZE 3 + +#define STD_COM_FLAGS (ASYNC_SKIP_TEST) + +#define STD_SERIAL_PORT_DEFNS \ + { \ + .uart = PORT_OMAP, \ + .baud_base = BASE_BAUD, \ + .iomem_base = OMAP1510_UART1_BASE, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + .irq = INT_UART1, \ + .flags = STD_COM_FLAGS, \ + }, { \ + .uart = PORT_OMAP, \ + .baud_base = BASE_BAUD, \ + .iomem_base = OMAP1510_UART2_BASE, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + .irq = INT_UART2, \ + .flags = STD_COM_FLAGS, \ + }, { \ + .uart = PORT_OMAP, \ + .baud_base = BASE_BAUD, \ + .iomem_base = OMAP1510_UART3_BASE, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + .irq = INT_UART3, \ + .flags = STD_COM_FLAGS, \ + } +#endif /* CONFIG_ARCH_OMAP730 */ + +#define EXTRA_SERIAL_PORT_DEFNS + +/* OMAP FCR trigger redefinitions */ +#define UART_FCR_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 8 */ +#define UART_FCR_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 16 */ +#define UART_FCR_R_TRIGGER_56 0x80 /* Mask for receive trigger set at 56 */ +#define UART_FCR_R_TRIGGER_60 0xC0 /* Mask for receive trigger set at 60 */ + +/* There is an error in the description of the transmit trigger levels of + OMAP5910 TRM from January 2003. The transmit trigger level 56 is not + 56 but 32, the transmit trigger level 60 is not 60 but 56! + Additionally, the descritption of these trigger levels is + a little bit unclear. The trigger level define the number of EMPTY + entries in the FIFO. Thus, if TRIGGER_8 is used, an interrupt is requested + if 8 FIFO entries are empty (and 56 entries are still filled [the FIFO + size is 64]). Or: If TRIGGER_56 is selected, everytime there are less than + 8 characters in the FIFO, an interrrupt is spawned. In other words: The + trigger number is equal the number of characters which can be + written without FIFO overrun */ + +#define UART_FCR_T_TRIGGER_8 0x00 /* Mask for transmit trigger set at 8 */ +#define UART_FCR_T_TRIGGER_16 0x10 /* Mask for transmit trigger set at 16 */ +#define UART_FCR_T_TRIGGER_32 0x20 /* Mask for transmit trigger set at 32 */ +#define UART_FCR_T_TRIGGER_56 0x30 /* Mask for transmit trigger set at 56 */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_SERIAL_H */ diff -Nru a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/system.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,20 @@ +/* + * Copied from linux/include/asm-arm/arch-sa1100/system.h + * Copyright (c) 1999 Nicolas Pitre + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H +#include +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + *(volatile u16 *)(ARM_RSTCT1) = 1; +} + +#endif diff -Nru a/include/asm-arm/arch-omap/time.h b/include/asm-arm/arch-omap/time.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/time.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,212 @@ +/* + * linux/include/asm-arm/arch-omap/time.h + * + * 32kHz timer definition + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#if !defined(__ASM_ARCH_OMAP_TIME_H) +#define __ASM_ARCH_OMAP_TIME_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef __instrument +#define __instrument +#define __noinstrument __attribute__ ((no_instrument_function)) +#endif + +typedef struct { + u32 cntl; /* CNTL_TIMER, R/W */ + u32 load_tim; /* LOAD_TIM, W */ + u32 read_tim; /* READ_TIM, R */ +} mputimer_regs_t; + +#define mputimer_base(n) \ + ((volatile mputimer_regs_t*)(OMAP_MPUTIMER_BASE + \ + (n)*OMAP_MPUTIMER_OFF)) + +static inline unsigned long timer32k_read(int reg) { + unsigned long val; + val = (inw(IO_ADDRESS((reg) + OMAP_32kHz_TIMER_BASE))); + return val; +} +static inline void timer32k_write(int reg,int val) { + outw( (val), (IO_ADDRESS( (reg) + OMAP_32kHz_TIMER_BASE))); +} + +/* + * How long is the timer interval? 100 HZ, right... + * IRQ rate = (TVR + 1) / 32768 seconds + * TVR = 32768 * IRQ_RATE -1 + * IRQ_RATE = 1/100 + * TVR = 326 + */ +#define TIMER32k_PERIOD 326 +//#define TIMER32k_PERIOD 0x7ff + +static inline void start_timer32k(void) { + timer32k_write(TIMER32k_CR, + TIMER32k_TSS | TIMER32k_TRB | + TIMER32k_INT | TIMER32k_ARL); +} + +#ifdef CONFIG_MACH_OMAP_PERSEUS2 +/* + * After programming PTV with 0 and setting the MPUTIM_CLOCK_ENABLE + * (external clock enable) bit, the timer count rate is 6.5 MHz (13 + * MHZ input/2). !! The divider by 2 is undocumented !! + */ +#define MPUTICKS_PER_SEC (13000000/2) +#else +/* + * After programming PTV with 0, the timer count rate is 6 MHz. + * WARNING! this must be an even number, or machinecycles_to_usecs + * below will break. + */ +#define MPUTICKS_PER_SEC (12000000/2) +#endif + +static int mputimer_started[3] = {0,0,0}; + +static inline void __noinstrument start_mputimer(int n, + unsigned long load_val) +{ + volatile mputimer_regs_t* timer = mputimer_base(n); + + mputimer_started[n] = 0; + timer->cntl = MPUTIM_CLOCK_ENABLE; + udelay(1); + + timer->load_tim = load_val; + udelay(1); + timer->cntl = (MPUTIM_CLOCK_ENABLE | MPUTIM_AR | MPUTIM_ST); + mputimer_started[n] = 1; +} + +static inline unsigned long __noinstrument +read_mputimer(int n) +{ + volatile mputimer_regs_t* timer = mputimer_base(n); + return (mputimer_started[n] ? timer->read_tim : 0); +} + +void __noinstrument start_mputimer1(unsigned long load_val) +{ + start_mputimer(0, load_val); +} +void __noinstrument start_mputimer2(unsigned long load_val) +{ + start_mputimer(1, load_val); +} +void __noinstrument start_mputimer3(unsigned long load_val) +{ + start_mputimer(2, load_val); +} + +unsigned long __noinstrument read_mputimer1(void) +{ + return read_mputimer(0); +} +unsigned long __noinstrument read_mputimer2(void) +{ + return read_mputimer(1); +} +unsigned long __noinstrument read_mputimer3(void) +{ + return read_mputimer(2); +} + +unsigned long __noinstrument do_getmachinecycles(void) +{ + return 0 - read_mputimer(0); +} + +unsigned long __noinstrument machinecycles_to_usecs(unsigned long mputicks) +{ + /* Round up to nearest usec */ + return ((mputicks * 1000) / (MPUTICKS_PER_SEC / 2 / 1000) + 1) >> 1; +} + +/* + * This marks the time of the last system timer interrupt + * that was *processed by the ISR* (timer 2). + */ +static unsigned long systimer_mark; + +static unsigned long omap1510_gettimeoffset(void) +{ + /* Return elapsed usecs since last system timer ISR */ + return machinecycles_to_usecs(do_getmachinecycles() - systimer_mark); +} + +static irqreturn_t +omap1510_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned long now, ilatency; + + /* + * Mark the time at which the timer interrupt ocurred using + * timer1. We need to remove interrupt latency, which we can + * retrieve from the current system timer2 counter. Both the + * offset timer1 and the system timer2 are counting at 6MHz, + * so we're ok. + */ + now = 0 - read_mputimer1(); + ilatency = MPUTICKS_PER_SEC / 100 - read_mputimer2(); + systimer_mark = now - ilatency; + + do_leds(); + do_timer(regs); + do_profile(regs); + + return IRQ_HANDLED; +} + +void __init time_init(void) +{ + /* Since we don't call request_irq, we must init the structure */ + gettimeoffset = omap1510_gettimeoffset; + + timer_irq.handler = omap1510_timer_interrupt; + timer_irq.flags = SA_INTERRUPT; +#ifdef OMAP1510_USE_32KHZ_TIMER + timer32k_write(TIMER32k_CR, 0x0); + timer32k_write(TIMER32k_TVR,TIMER32k_PERIOD); + setup_irq(INT_OS_32kHz_TIMER, &timer_irq); + start_timer32k(); +#else + setup_irq(INT_TIMER2, &timer_irq); + start_mputimer2(MPUTICKS_PER_SEC / 100 - 1); +#endif +} + +#endif diff -Nru a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/timex.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/timex.h + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#if !defined(__ASM_ARCH_OMAP_TIMEX_H) +#define __ASM_ARCH_OMAP_TIMEX_H + +#include +/* TC clock */ +#define CLOCK_TICK_RATE ((OMAP_CK_MAX_RATE*1000000)/2) + +#endif /* __ASM_ARCH_OMAP_TIMEX_H */ diff -Nru a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/uncompress.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,76 @@ +/* + * linux/include/asm-arm/arch-omap/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Initially based on: + * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon + * + * Rewritten by: + * Author: + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + + +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) + +static void +puts(const char *s) +{ + volatile u8 * uart = 0; + int shift = 0; + + /* Determine which serial port to use */ + do { + if (machine_is_innovator()) { + shift = 2; + uart = (volatile u8 *)(OMAP1510_UART1_BASE); + } else { + /* Assume nothing for unknown machines. + * Add an entry for your machine to select + * the default serial console here. If the + * serial port is enabled, we'll use it to + * display status messages. Else we'll be + * quiet. + */ + return; + } + if (check_port(uart, shift)) + break; + /* Silent boot if no serial ports are enabled. */ + return; + } while (0); + + /* + * Now, xmit each character + */ + while (*s) { + while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + barrier(); + uart[UART_TX << shift] = *s; + if (*s++ == '\n') { + while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + barrier(); + uart[UART_TX << shift] = '\r'; + } + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff -Nru a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-arm/arch-omap/vmalloc.h Sun Apr 4 18:51:05 2004 @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) + +#define MODULE_START (PAGE_OFFSET - 16*1048576) +#define MODULE_END (PAGE_OFFSET) diff -Nru a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h --- a/include/asm-arm/arch-pxa/memory.h Sun Apr 4 18:51:05 2004 +++ b/include/asm-arm/arch-pxa/memory.h Sun Apr 4 18:51:05 2004 @@ -55,4 +55,52 @@ #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) +#ifdef CONFIG_DISCONTIGMEM +/* + * The nodes are matched with the physical SDRAM banks as follows: + * + * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff + * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff + * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff + * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff + */ + +#define NR_NODES 4 + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26) + +/* + * Given a page frame number, convert it to a node id. + */ +#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) + +/* + * Given a page frame number, find the owning node of the memory + * and returns the mem_map of that node. + */ +#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT) + +#else + +#define PFN_TO_NID(addr) (0) + +#endif + #endif diff -Nru a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h --- a/include/asm-arm/arch-pxa/pxa-regs.h Sun Apr 4 18:51:05 2004 +++ b/include/asm-arm/arch-pxa/pxa-regs.h Sun Apr 4 18:51:05 2004 @@ -1076,6 +1076,35 @@ #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ +#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ +#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ +#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ +#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ +#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ +#define SSCR0_National (0x2 << 4) /* National Microwire */ +#define SSCR0_ECS (1 << 6) /* External clock select */ +#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ +#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ +#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ + +#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ +#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ +#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ +#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ +#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ +#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ + +#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ +#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ +#define SSSR_BSY (1 << 4) /* SSP Busy */ +#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ +#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ +#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ + /* * MultiMediaCard (MMC) controller diff -Nru a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h --- a/include/asm-arm/cacheflush.h Sun Apr 4 18:51:05 2004 +++ b/include/asm-arm/cacheflush.h Sun Apr 4 18:51:05 2004 @@ -41,7 +41,7 @@ #endif #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ - defined(CONFIG_CPU_ARM1020) + defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) # define MULTI_CACHE 1 #endif diff -Nru a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h --- a/include/asm-arm/proc-fns.h Sun Apr 4 18:51:05 2004 +++ b/include/asm-arm/proc-fns.h Sun Apr 4 18:51:05 2004 @@ -66,6 +66,14 @@ # define CPU_NAME cpu_arm922 # endif # endif +# ifdef CONFIG_CPU_ARM925T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm925 +# endif +# endif # ifdef CONFIG_CPU_ARM926T # ifdef CPU_NAME # undef MULTI_CPU