From: Linus Torvalds From: Steven Rostedt Remove the Intel quirk entirely, and replaces it with the "if there's no resource, use the parent resource as the default fallback" code. Here's a very very slightly changed patch. The only addition is to make the extra line of b->resource[2] = &iomem_resource; which makes the root PCI device have "iomem_resource" for both it's prefetchable and non-prefetchable resource. That's damn subtle, but it means that it the non-prefetchable one is overridden by a half-transparent setup like I have, then in order to see a prefetchable area at all, you want that root iomem_resource to "shine through" the transparent prefetchable region. Signed-off-by: Andrew Morton --- 25-akpm/arch/i386/pci/fixup.c | 17 ----------------- 25-akpm/drivers/pci/probe.c | 25 +++++++++++++++++-------- 2 files changed, 17 insertions(+), 25 deletions(-) diff -puN arch/i386/pci/fixup.c~pcmcia-bridge-resource-management-fix arch/i386/pci/fixup.c --- 25/arch/i386/pci/fixup.c~pcmcia-bridge-resource-management-fix 2005-02-19 23:52:32.000000000 -0800 +++ 25-akpm/arch/i386/pci/fixup.c 2005-02-19 23:52:32.000000000 -0800 @@ -197,23 +197,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_V DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); /* - * For some reasons Intel decided that certain parts of their - * 815, 845 and some other chipsets must look like PCI-to-PCI bridges - * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, - * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according - * to Intel terminology. These devices do forward all addresses from - * system to PCI bus no matter what are their window settings, so they are - * "transparent" (or subtractive decoding) from programmers point of view. - */ -static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev) -{ - if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && - (dev->device & 0xff00) == 0x2400) - dev->transparent = 1; -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge); - -/* * Fixup for C1 Halt Disconnect problem on nForce2 systems. * * From information provided by "Allen Martin" : diff -puN drivers/pci/probe.c~pcmcia-bridge-resource-management-fix drivers/pci/probe.c --- 25/drivers/pci/probe.c~pcmcia-bridge-resource-management-fix 2005-02-19 23:52:32.000000000 -0800 +++ 25-akpm/drivers/pci/probe.c 2005-02-19 23:52:32.000000000 -0800 @@ -243,17 +243,20 @@ void __devinit pci_read_bridge_bases(str if (!dev) /* It's a host bus, nothing to read */ return; + /* + * We default to the parent resources, and override them only + * if this device has its own range defined. + */ + for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) + child->resource[i] = child->parent->resource[i]; + if (dev->transparent) { printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev)); - for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) - child->resource[i] = child->parent->resource[i]; return; } - for(i=0; i<3; i++) - child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; - - res = child->resource[0]; + /* Resource 0 - IO ports */ + res = &dev->resource[PCI_BRIDGE_RESOURCES+0]; pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; @@ -271,9 +274,11 @@ void __devinit pci_read_bridge_bases(str res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; res->start = base; res->end = limit + 0xfff; + child->resource[0] = res; } - res = child->resource[1]; + /* Resource 1 - nonprefetchable memory resource */ + res = &dev->resource[PCI_BRIDGE_RESOURCES+1]; pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; @@ -282,9 +287,11 @@ void __devinit pci_read_bridge_bases(str res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; res->start = base; res->end = limit + 0xfffff; + child->resource[1] = res; } - res = child->resource[2]; + /* Resource 2 - prefetchable memory resource */ + res = &dev->resource[PCI_BRIDGE_RESOURCES+2]; pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; @@ -316,6 +323,7 @@ void __devinit pci_read_bridge_bases(str res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; res->start = base; res->end = limit + 0xfffff; + child->resource[2] = res; } } @@ -913,6 +921,7 @@ struct pci_bus * __devinit pci_scan_bus_ b->number = b->secondary = bus; b->resource[0] = &ioport_resource; b->resource[1] = &iomem_resource; + b->resource[2] = &iomem_resource; b->subordinate = pci_scan_child_bus(b); _