From: "Antonino A. Daplas" This is a work around for the 830M with intelfb. Relative to 2.6.10. Without this patch, updates to the DSPACNTR register will be ignored. On the 830M, the display plane needs to be enabled before writing to any of the other bits in the DSPACNTR register. This patch detects the specific case, temporarily enables the plane, updates the register, and then disables the plane. It also appears to require some settling time, but not an entire frame's time. Without this change, the pixel format fields in DSPACNTR won't get written on the 830M. Signed-off-by: Andrew Pfiffer Signed-off-by: Antonino Daplas Signed-off-by: Andrew Morton --- 25-akpm/drivers/video/intelfb/intelfbhw.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+) diff -puN drivers/video/intelfb/intelfbhw.c~intelfb-workaround-for-830m drivers/video/intelfb/intelfbhw.c --- 25/drivers/video/intelfb/intelfbhw.c~intelfb-workaround-for-830m Tue Jan 18 15:04:28 2005 +++ 25-akpm/drivers/video/intelfb/intelfbhw.c Tue Jan 18 15:04:28 2005 @@ -1207,6 +1207,22 @@ intelfbhw_program_mode(struct intelfb_in OUTREG(ADPA, tmp); /* setup display plane */ + if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) { + /* + * i830M errata: the display plane must be enabled + * to allow writes to the other bits in the plane + * control register. + */ + tmp = INREG(DSPACNTR); + if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) { + tmp |= DISPPLANE_PLANE_ENABLE; + OUTREG(DSPACNTR, tmp); + OUTREG(DSPACNTR, + hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); + mdelay(1); + } + } + OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); OUTREG(DSPASTRIDE, hw->disp_a_stride); OUTREG(DSPABASE, hw->disp_a_base); _